Added Hazard Unit file (tested compiling correctly) labelled variables inside off of the Assignment 3 Questions PDF Figure 2.

Also have a placeholder MUX to place before the ALU for adding hazard unit functionality
Fixed bug in test code where there was a hazzard, despite testing assuming no hazzard. Updated testbench to reflect this (Ln57-62).
2026-11-08 12:32:40 +11:00 · 2026-11-05 16:15:06 +11:00 · 2026-11-05 15:46:05 +11:00 · 2026-11-05 14:33:41 +11:00 · 2026-11-05 14:27:01 +11:00 · 2026-11-05 14:25:34 +11:00
293 changed files with 433364 additions and 8836 deletions
@@ -41,7 +41,7 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 Top level modules:
 	control_unit

-} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
 -- Compiling module rom
 -- Compiling module ram
@@ -52,9 +52,6 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 -- Compiling module asu
 -- Compiling module lu
 -- Compiling module alu
-** Warning: ** while parsing file included at /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(1)
-** while parsing file included at assignment2.sv(9)
-** at alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block.
 -- Compiling module shifter
 -- Compiling module sign_extender
 -- Compiling module seven_seg
@@ -64,6 +61,7 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb

 Top level modules:
 	shifter
+	seven_seg_4digit
 	mips_tb

 } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv
@@ -88,7 +86,7 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 Top level modules:
 	shifter_tb

-} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv
 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
 -- Compiling module rom
 -- Compiling module ram
@@ -99,8 +97,6 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 -- Compiling module asu
 -- Compiling module lu
 -- Compiling module alu
-** Warning: ** while parsing file included at /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv(9)
-** at alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block.
 -- Compiling module shifter
 -- Compiling module sign_extender
 -- Compiling module seven_seg
@@ -109,6 +105,7 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb

 Top level modules:
 	shifter
+	seven_seg_4digit
 	assignment2

 } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
@@ -135,6 +132,16 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 Top level modules:
 	lu_tb

+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module asu
+-- Compiling module lu
+-- Compiling module alu
+-- Compiling module alu_tb
+
+Top level modules:
+	alu_tb
+
 } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
 -- Compiling module sign_extender
@@ -142,17 +149,19 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 Top level modules:
 	sign_extender

-} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/gatereg.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/gatereg.sv
 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module asu
-- Compiling module lu
-- Compiling module alu
-** Warning: ** while parsing file included at /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv(1)
-** at alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block.
-- Compiling module alu_tb
+-- Compiling module gatereg

 Top level modules:
-	alu_tb
+	gatereg
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/hazard_unit.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/hazard_unit.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module hazard_unit
+
+Top level modules:
+	hazard_unit

 } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv
 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
@@ -161,12 +170,11 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 Top level modules:
 	instruction_counter

-} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
 -- Compiling module asu
 -- Compiling module lu
 -- Compiling module alu
-** Warning: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block.

 Top level modules:
 	alu
@@ -180,14 +188,6 @@ Top level modules:
 	rom
 	ByteIM

-} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module seven_seg
-- Compiling module seven_seg_4digit
-
-Top level modules:
-	seven_seg_4digit
-
 } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
 -- Compiling module instruction_classifier
@@ -196,6 +196,14 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 Top level modules:
 	instruction_classifier_tb

+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module seven_seg
+-- Compiling module seven_seg_4digit
+
+Top level modules:
+	seven_seg_4digit
+
 } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
 -- Compiling module register_file
@@ -203,4 +211,24 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 Top level modules:
 	register_file

+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module rom
+-- Compiling module ram
+-- Compiling module register_file
+-- Compiling module instruction_counter
+-- Compiling module instruction_classifier
+-- Compiling module control_unit
+-- Compiling module asu
+-- Compiling module lu
+-- Compiling module alu
+-- Compiling module shifter
+-- Compiling module sign_extender
+-- Compiling module gatereg
+-- Compiling module assignment3
+
+Top level modules:
+	shifter
+	assignment3
+
 } {} {}}
@@ -220,7 +220,7 @@ Resolution = ps
 UserTimeUnit = default

 ; Default run length
-RunLength = 1 ns
+RunLength = 1 us

 ; Maximum iterations that can be run without advancing simulation time
 IterationLimit = 5000
@@ -410,51 +410,57 @@ ConcurrentFileLimit = 40
 Project_Version = 6
 Project_DefaultLib = work
 Project_SortMethod = unused
-Project_Files_Count = 22
+Project_Files_Count = 25
 Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv
-Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv
-Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792107144 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_2 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv
-Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_3 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv
-Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_4 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv
-Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792039197 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792473740 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_5 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/control_unit.sv
-Project_File_P_5 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792040117 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_5 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792112234 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_6 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
-Project_File_P_6 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792104861 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_6 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1792115823 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_7 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv
-Project_File_P_7 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228118 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_7 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228118 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_8 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv
-Project_File_P_8 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_8 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_9 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv
-Project_File_P_9 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789513270 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_9 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789513270 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_10 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv
-Project_File_P_10 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792106709 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_10 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792119882 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_11 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
-Project_File_P_11 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788418794 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 18 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_11 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788418794 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 18 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_12 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
-Project_File_P_12 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789513270 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_12 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789513270 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_13 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
-Project_File_P_13 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788926090 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_13 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788926090 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_14 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
-Project_File_P_14 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792038654 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 21 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_14 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792644107 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_15 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
-Project_File_P_15 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_16 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv
-Project_File_P_16 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1791854498 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_17 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
-Project_File_P_17 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792036226 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_18 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv
-Project_File_P_18 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792106811 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_19 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
-Project_File_P_19 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1791866874 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_20 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
-Project_File_P_20 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_21 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
-Project_File_P_21 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792035553 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_15 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_16 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/gatereg.sv
+Project_File_P_16 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1793848262 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 23 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_17 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/hazard_unit.sv
+Project_File_P_17 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1794101042 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 24 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_18 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv
+Project_File_P_18 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_19 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
+Project_File_P_19 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792115823 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_20 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv
+Project_File_P_20 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1793848949 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_21 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
+Project_File_P_21 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792119097 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_22 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
+Project_File_P_22 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_23 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
+Project_File_P_23 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792112234 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_24 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv
+Project_File_P_24 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1793848882 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 22 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_Sim_Count = 0
 Project_Folder_Count = 0
 Echo_Compile_Output = 0
@@ -0,0 +1,14 @@
+`include "rom.sv"
+
+module ByteIM #(parameter m=5,n=2) (
+    input logic [m-1:0] Ad,
+    output logic [(2**n)*8-1:0] Dout );
+
+    // 2**n byte wide words
+    // m bit wide byte address
+    // 2**m bytes of memory
+    // 2**(m-n) memory words
+    // 2**(n+3) bit wide words
+    // Reads the whole word that contains the addressed byte
+    ROM #(m-n,2**(n+3)) wordrom(Ad[m-1:n],Dout)
+endmodule
@@ -6,6 +6,7 @@

 // flags[0:0] = Cout
 // flags[1:1] = Overflow
+// flags[2:2] = Zero
 module alu #(parameter width=2)(input logic [3:0] op,
    input logic [2**width-1:0] A, input logic [2**width-1:0] B,
    output logic [2**width-1:0] OUT_1, output logic[2:0] flags
@@ -15,26 +16,30 @@ module alu #(parameter width=2)(input logic [3:0] op,
    logic [2**width-1:0] asu_out;
    logic [2:0] asu_flags;

-    asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
+    assign asu_op = op[1];
+    logic [0:0] asu_cout_flag;
+    asu #(width) adder_unit(asu_op, A, B, asu_out, asu_flags[0], asu_cout_flag);

    logic [2**width-1:0] lu_out;
    lu #(width) logic_unit(op[1:0], A, B, lu_out);

+    assign asu_flags[1] = asu_cout_flag ^ asu_flags[0];
    always_comb begin
        case (op) 
-            4'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
-            4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
-            4'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
-            4'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
-            4'b0100: begin OUT_1 = lu_out; flags = asu_flags; end
-            4'b0101: begin OUT_1 = lu_out; flags = asu_flags; end
-            4'b0110: begin OUT_1 = lu_out;  flags = asu_flags; end
-            4'b0111: begin OUT_1 = lu_out; flags = asu_flags; end
-            4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
-            4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
-            default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
+            4'b0000: begin OUT_1 = asu_out; end
+            4'b0001: begin OUT_1 = asu_out; end
+            4'b0010: begin OUT_1 = asu_out; end
+            4'b0011: begin OUT_1 = asu_out; end
+            4'b0100: begin OUT_1 = lu_out; end
+            4'b0101: begin OUT_1 = lu_out; end
+            4'b0110: begin OUT_1 = lu_out; end
+            4'b0111: begin OUT_1 = lu_out; end
+            4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; end
+            4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; end
+            default: begin OUT_1 = {(2**width){1'b0}}; end
        endcase
        asu_flags[2] = OUT_1 == 0;
+        flags = asu_flags;
    end
 endmodule
 `endif
@@ -0,0 +1,20 @@
+`include "asu.v"
+`include "lu.v"
+
+// flags[0:0] = Cout
+// flags[1:1] = Overflow
+module alu #(width=8)(input logic [3:0] op,
+    input logic [width-1:0] A, input logic [width-1:0] B.
+    output logic [width-1:0] OUT_1, output logic flags[1:0]);
+
+    logic [width-1:0] asu_out;
+    logic [1:0] asu_flags;
+    logic [0:0] asu_op;
+    asu #(width) adder_unit(asu_op, A, B, asu_out, asu_flags[0], asu_flags[1]);
+
+    logic [width-1:0] lu_out;
+    lu #(width) logic_unit(op[1:0], A, B, lu_out);
+
+    // Cout = asu_flags[0]
+    // Overflow = asu_flags[0] ^ asu_flags[1]
+endmodule
@@ -13,7 +13,9 @@


 module assignment2 #(width=5, ramsz=9, romsz=10) (
-	input logic [0:0] clk,
+	input logic [0:0] clk, input logic [0:0] rst
+`ifdef QUARTUS_SYNTH
+    ,
 	input logic [4:0] HID_Register,
 	input logic [0:0] HID_PC,
 	input logic [0:0] HID_Hi_Low,
@@ -22,13 +24,14 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	output logic[7:0] out_seg_1,
 	output logic[7:0] out_seg_2,
 	output logic[7:0] out_seg_3
+`endif
 	);
 	// Intermediate for displaying high / low of PC or Register
 	logic[15:0] PC_Reg_Display;
 	
 	// Program / Instruction Counter Intermediates
-	logic [romsz-1:0] pc_addr;
-	logic [romsz-1:0] pc_addr_write;
+	logic [2**width-1:0] pc_addr;
+	logic [2**width-1:0] pc_addr_write;
 	logic [0:0] pc_we;
 	logic [2**width-1:0] instruction;
 	
@@ -49,16 +52,16 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	logic [0:0] rd_we;
 	logic [31:0] regs_out [32];

-    // ALU intermeduates
+    // ALU intermediates
 	logic [2**width-1:0] rd_alu;
 	logic [2**width-1:0] rt_alu;
 	
-	instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
+	instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
 	
-	rom #(romsz, 2**width) ROM (pc_addr, instruction);
+	rom #(romsz, width) ROM (pc_addr, instruction);

 	logic [2**width-1:0] rd_mem;
-	ram #(ramsz, 2**width) RAM (clk, rd_alu, M2W, rt, rd_mem);
+	ram #(ramsz, width) RAM (clk, rst, rd_alu, M2W, rt, rd_mem);
 	
 	control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
 		M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW
@@ -67,32 +70,36 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (

 	register_file #(width, 5) REGS (
 		clk, rd_we, 
-		instruction[20:16], rd,
-		(RDST) ? instruction[15:11] : instruction[20:16], rt,
+		(RDST) ? instruction[15:11] : instruction[20:16], rd,
 		instruction[25:21], rs,
+		instruction[20:16], rt, 
 		regs_out
   );
    // Always use sign-extension
    logic [2**width-1:0] rt_imm;
    sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], rt_imm);
-    // TODO:
-    //  - ALU srcB
-    //  - PCBranch (rel jump of 4-byte words)

-	alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags[1:0]);
+	alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags);
    assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt);

 	assign pc_we = B & flags[2];
 	assign pc_addr_write = (rt_imm << 2) + pc_addr;
 	assign rd_we = RW;
-	assign rd = (M2R) ? rd_alu : rd_mem;
-
+	assign rd = (M2R) ? rd_mem : rd_alu;


+`ifdef QUARTUS_SYNTH
 	// Temporary Test output
 	// assign PC_Reg_Display = 16'hC342;
-
-   assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0];
+	// assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0];
+	always_comb begin
+		if (HID_PC == 1'b1) begin
+			PC_Reg_Display = (HID_Hi_Low) ? pc_addr[31:16] : pc_addr[15:0];
+		end
+		else begin
+			PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0];
+		end	
+	end
 	
 	seven_seg_4digit display (
 		.num(PC_Reg_Display),
@@ -101,6 +108,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 		.segments2(out_seg_2),
 		.segments3(out_seg_3)
 	);
+`endif // code for board test outputs only

 endmodule
 `endif
@@ -0,0 +1,19 @@
+`include "rom.sv"
+`include "ram.sv"
+`include "instruction_counter.sv"
+`include "instruction_classifier.sv"
+`include "alu.sv"
+
+
+module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
+    
+    logic [romsz-1:0] pc_addr;
+    logic [0:0] pc_we;
+    logic [2**width-1:0] instruction;
+
+    instruction_counter pc #(romsz)(clk, pc_we, pc_addr, pc_addr);
+    ROM rom #(romsz, 2**width)();
+    RAM ram #(ramsz,  2**width)();
+    alu alu #(width)();
+
+endmodule
@@ -0,0 +1,95 @@
+`ifndef ASS_3_SV
+`define ASS_3_SV
+
+`include "rom.sv"
+`include "ram.sv"
+`include "register_file.sv"
+`include "instruction_counter.sv"
+`include "control_unit.sv"
+`include "alu.sv"
+`include "shifter.sv"
+`include "sign_extender.sv"
+`include "gatereg.sv"
+
+module assignment3 #(width=5, romsz=9, ramsz=10)(
+	input logic [0:0] clk, input logic [0:0] rst
+	);
+	logic [31:0] regs_out [32];
+	logic [2**width-1:0] pc_addr, pc_addr_2;
+	logic [2**width-1:0] pc_addr_write;
+	logic [0:0] pc_we;
+	// TODO: Verify if we need a clk gating on pc_addr
+	instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
+	gatereg #(width, 2) gate_pc_addr_1(clk, rst, 1'b1, pc_addr, pc_addr_2);
+
+
+	logic [2**width-1:0] rom_rd;
+	logic [2**width-1:0] rom_addr;
+	logic [2**width-1:0] instruction, instruction_1;
+	rom #(romsz, width) ROM (rom_addr[romsz-1:0], rom_rd);
+	gatereg #(width, 1) gate_pc_addr(clk, rst, 1'b1, pc_addr, rom_addr);
+	gatereg #(width, 1) gate_instruction(clk, rst, 1'b1, rom_rd, instruction);
+	gatereg #(width, 1) gate_instruction_1(clk, rst, 1'b1, instruction, instruction_1);
+
+
+	logic [0:0] cu_m2r, cu_m2w, cu_b, cu_alu_src, cu_rdst, cu_rw;
+	logic [3:0] cu_alu_fn, ALU_FN;
+	logic [0:0] B, MEM_WE, RDST, ALU_SRC, REG_WE, REGW_MEM_OR_RD;
+	control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
+		cu_m2r, cu_m2w, cu_b, cu_alu_fn, cu_alu_src, cu_rdst, cu_rw
+	);
+	gatereg #(0, 1) gate_cu_rdst (clk, rst, 1'b1, cu_rdst, RDST);
+	gatereg #(0, 1) gate_cu_alu_src (clk, rst, 1'b1, cu_alu_src, ALU_SRC);
+	gatereg #(2, 1) gate_cu_alu_fn (clk, rst, 1'b1, cu_alu_fn, ALU_FN);
+
+	gatereg #(0, 2) gate_cu_b (clk, rst, 1'b1, cu_b, B);
+	gatereg #(0, 2) gate_cu_m2w (clk, rst, 1'b1, cu_m2w, MEM_WE);
+	
+	gatereg #(0, 3) gate_cu_rw (clk, rst, 1'b1, cu_rw, REG_WE);
+	gatereg #(0, 3) gate_cu_m2r (clk, rst, 1'b1, cu_m2r, REGW_MEM_OR_RD);
+	
+	logic [2**width-1:0] regf_rs, regf_rs_1;
+	logic [2**width-1:0] regf_rt, regf_rt_1, regf_rt_2;
+	logic [7:0] regf_a3, regf_a3_2;
+	logic [2**width-1:0] rd, rd_mem, rd_alu;
+	assign rd = (REGW_MEM_OR_RD) ? rd_mem : rd_alu;
+	assign regf_a3 = (RDST) ? instruction_1[15:11] : instruction_1[20:16];
+	// TODO: Connect inputs
+	gatereg #(3, 2) gate_regf_a3 (clk, rst, 1'b1, regf_a3, regf_a3_2);
+	register_file #(width, 5) REGS (
+		~clk, REG_WE, 
+		regf_a3_2[4:0], rd,
+		instruction[25:21], regf_rs,
+		instruction[20:16], regf_rt,
+		regs_out
+	);
+	gatereg #(width, 1) gate_regf_rs(clk, rst, 1'b1, regf_rs, regf_rs_1);
+	gatereg #(width, 1) gate_regf_rt(clk, rst, 1'b1, regf_rt, regf_rt_1);
+	gatereg #(width, 1) gate_regf_rt_1(clk, rst, 1'b1, regf_rt_1, regf_rt_2);
+	
+	logic [2**width-1:0] sign_ext_imm, rt_imm;
+	sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], sign_ext_imm);
+	gatereg #(width, 1) gate_sign_ext_imm(clk, rst, 1'b1, sign_ext_imm, rt_imm);
+
+
+	logic [2**width-1:0] alu_out, alu_out_1, alu_out_2;
+	logic [3:0] alu_flags, alu_flags_1;
+	alu #(width) ALU (ALU_FN, regf_rs_1, (ALU_SRC) ? rt_imm : regf_rt_1, alu_out, alu_flags);
+	gatereg #(width, 1) gate_alu_out (clk, rst, 1'b1, alu_out, alu_out_1);
+	gatereg #(width, 1) gate_alu_out_1 (clk, rst, 1'b1, alu_out_1, alu_out_2);
+	gatereg #(width, 1) gate_alu_flags (clk, rst, 1'b1, alu_flags, alu_flags_1);
+	assign rd_alu = alu_out_2;
+
+	logic [2**width-1:0] new_pc_addr, new_pc_addr_1;
+	assign new_pc_addr = (rt_imm << 2) + pc_addr_2;
+	gatereg #(width, 1) gate_new_pc_addr (clk, rst, 1'b1, new_pc_addr, new_pc_addr_1);
+	
+
+	assign pc_addr_write = new_pc_addr_1;
+	assign pc_we = B & alu_flags_1[2];
+	logic [2**width-1:0] mem_out, mem_out_1;
+	ram #(ramsz, width) RAM (clk, rst, alu_out_1, MEM_WE, regf_rt_2, mem_out);
+	gatereg #(width, 1) gate_mem_out (clk, rst, 1'b1, mem_out, mem_out_1);
+	assign rd_mem = mem_out_1;
+endmodule
+`endif
@@ -0,0 +1,95 @@
+`ifndef ASS_3_SV
+`define ASS_3_SV
+
+`include "rom.sv"
+`include "ram.sv"
+`include "register_file.sv"
+`include "instruction_counter.sv"
+`include "control_unit.sv"
+`include "alu.sv"
+`include "shifter.sv"
+`include "sign_extender.sv"
+`include "gatereg.sv"
+
+module assignment3 #(width=5, romsz=9, ramsz=10)(
+    input logic [0:0] clk, input logic [0:0] rst
+	);
+	logic [31:0] regs_out [32];
+	logic [2**width-1:0] pc_addr, pc_addr_2;
+	logic [2**width-1:0] pc_addr_write;
+	logic [0:0] pc_we;
+	// TODO: Verify if we need a clk gating on pc_addr
+	instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
+	gatereg #(width, 2) gate_pc_addr_1(clk, rst, 1'b1, pc_addr, pc_addr_2);
+
+
+	logic [2**width-1:0] rom_rd;
+	logic [2**width-1:0] rom_addr;
+	logic [2**width-1:0] instruction, instruction_1;
+	rom #(romsz, width) ROM (rom_addr[romsz-1:0], rom_rd);
+	gatereg #(width, 1) gate_pc_addr(clk, rst, 1'b1, pc_addr, rom_addr);
+	gatereg #(width, 1) gate_instruction(clk, rst, 1'b1, rom_rd, instruction);
+	gatereg #(width, 1) gate_instruction_1(clk, rst, 1'b1, instruction, instruction_1);
+
+
+	logic [0:0] cu_m2r, cu_m2w, cu_b, cu_alu_src, cu_rdst, cu_rw;
+	logic [3:0] cu_alu_fn, ALU_FN;
+	logic [0:0] B, MEM_WE, RDST, ALU_SRC, REG_WE, REGW_MEM_OR_RD;
+	control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
+		cu_m2r, cu_m2w, cu_b, cu_alu_fn, cu_alu_src, cu_rdst, cu_rw
+	);
+	gatereg #(0, 1) gate_cu_rdst (clk, rst, 1'b1, cu_rdst, RDST);
+	gatereg #(0, 1) gate_cu_alu_src (clk, rst, 1'b1, cu_alu_src, ALU_SRC);
+	gatereg #(2, 1) gate_cu_alu_fn (clk, rst, 1'b1, cu_alu_fn, ALU_FN);
+
+	gatereg #(0, 2) gate_cu_b (clk, rst, 1'b1, cu_b, B);
+	gatereg #(0, 2) gate_cu_m2w (clk, rst, 1'b1, cu_m2w, MEM_WE);
+	
+	gatereg #(0, 3) gate_cu_rw (clk, rst, 1'b1, cu_rw, REG_WE);
+	gatereg #(0, 3) gate_cu_m2r (clk, rst, 1'b1, cu_m2r, REGW_MEM_OR_RD);
+	
+	logic [2**width-1:0] regf_rs, regf_rs_1;
+	logic [2**width-1:0] regf_rt, regf_rt_1, regf_rt_2;
+	logic [7:0] regf_a3, regf_a3_2;
+	logic [2**width-1:0] rd, rd_mem, rd_alu;
+	assign rd = (REGW_MEM_OR_RD) ? rd_mem : rd_alu;
+	assign regf_a3 = (RDST) ? instruction_1[15:11] : instruction_1[20:16];
+	// TODO: Connect inputs
+	gatereg #(3, 2) gate_regf_a3 (clk, rst, 1'b1, regf_a3, regf_a3_2);
+	register_file #(width, 5) REGS (
+		~clk, REG_WE, 
+		regf_a3_2[4:0], rd,
+		instruction[25:21], regf_rs,
+		instruction[20:16], regf_rt,
+		regs_out
+	);
+	gatereg #(width, 1) gate_regf_rs(clk, rst, 1'b1, regf_rs, regf_rs_1);
+	gatereg #(width, 1) gate_regf_rt(clk, rst, 1'b1, regf_rt, regf_rt_1);
+	gatereg #(width, 1) gate_regf_rt_1(clk, rst, 1'b1, regf_rt_1, regf_rt_2);
+	
+	logic [2**width-1:0] sign_ext_imm, rt_imm;
+	sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], sign_ext_imm);
+	gatereg #(width, 1) gate_sign_ext_imm(clk, rst, 1'b1, sign_ext_imm, rt_imm);
+
+
+	logic [2**width-1:0] alu_out, alu_out_1, alu_out_2;
+	logic [3:0] alu_flags, alu_flags_1;
+	alu #(width) ALU (ALU_FN, regf_rs_1, (ALU_SRC) ? rt_imm : regf_rt_1, alu_out, alu_flags);
+	gatereg #(width, 1) gate_alu_out (clk, rst, 1'b1, alu_out, alu_out_1);
+	gatereg #(width, 1) gate_alu_out_1 (clk, rst, 1'b1, alu_out_1, alu_out_2);
+	gatereg #(width, 1) gate_alu_flags (clk, rst, 1'b1, alu_flags, alu_flags_1);
+	assign rd_alu = alu_out_2;
+
+	logic [2**width-1:0] new_pc_addr, new_pc_addr_1;
+	assign new_pc_addr = (rt_imm << 2) + pc_addr_2;
+	gatereg #(width, 1) gate_new_pc_addr (clk, rst, 1'b1, new_pc_addr, new_pc_addr_1);
+	
+
+	assign pc_addr_write = new_pc_addr_1;
+	assign pc_we = B & alu_flags_1[2];
+	logic [2**width-1:0] mem_out, mem_out_1;
+	ram #(ramsz, width) RAM (clk, rst, alu_out_1, MEM_WE, regf_rt_2, mem_out);
+	gatereg #(width, 1) gate_mem_out (clk, rst, 1'b1, mem_out, mem_out_1);
+	assign rd_mem = mem_out_1;
+endmodule
+`endif
@@ -0,0 +1,16 @@
+module asu #(width=8)(input logic [0:0] op,
+    input logic[width-1:0] A, input logic[width-1:0] B,
+    output logic[width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN);
+
+    logic [width-1:0] operand;
+    always_comb begin
+        // A + (sub) ? B : -B
+        // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
+        operand = (B ^ {(width){op}});
+        {COUT, OUT_1} = A + operand + {{(width-1){1'b0}}, op};
+    end
+
+    // Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
+    // Cin for width-2'th bit to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
+    assign OUT_CIN = A[width-1] ^ operand[width-1] ^ OUT_1[width-1];
+endmodule
@@ -23,13 +23,13 @@ module control_unit (
    instruction_classifier CLASSIFIER (op, TYPE_R, TYPE_B1, TYPE_J, TYPE_B2, TYPE_I, TYPE_F, TYPE_M);

    always_comb begin
-        M2R = TYPE_M & op[3];
-        M2W = TYPE_M & ~op[3];
+        M2R = TYPE_M & ~((op & 6'b001000) >> 3);
+        M2W = TYPE_M & ((op & 6'b001000) >> 3);
        B = TYPE_B1 | TYPE_B2 | TYPE_J;
-        ALU_FN = (func & {(6){TYPE_R}}) | ( {4'b0000, op[1:0]} & {(6){TYPE_I}});
-        ALU_SRC = TYPE_B1 | TYPE_B2 | TYPE_I | TYPE_M;
-        RDST = TYPE_I;  // Imm ops store back into rt
-        RW = TYPE_R | TYPE_I | (TYPE_M & op[3]); // All ALU R-type ops, Addi/Addiu ops, and memory loads
+        ALU_FN = (func & {(4){TYPE_R}}) | ( {2'b00, (op & 6'b000011)} & {(4){TYPE_I}}) | (4'b0010 & {4{TYPE_B1 | TYPE_B2}});
+        ALU_SRC = TYPE_I | TYPE_M;
+        RDST = TYPE_R;  // Imm ops store back into rt
+        RW = TYPE_R | TYPE_I | M2R;
    end

 endmodule
@@ -0,0 +1,21 @@
+module gatereg #(width, ndelay=1)(
+    input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] en,
+    input logic [2**width-1:0] in, output logic [2**width-1:0] out
+);
+    logic [2**width-1:0] hold_value[ndelay];
+
+    assign out = hold_value[ndelay-1];
+    always_ff @( posedge clk ) begin
+        if (rst) begin
+            for (integer i = 0; i < ndelay; ++i) begin
+                hold_value[i] <= {(2**width){1'b0}};
+            end
+        end else if (en) begin
+            hold_value[0] <= in;
+            for (integer i = 1; i < ndelay; ++i) begin
+                hold_value[i] <= hold_value[i-1];
+            end
+        end
+    end
+
+endmodule
@@ -0,0 +1,84 @@
+`ifndef HAZARD_SV
+`define HAZARD_SV
+
+module hazard_unit (
+    // (I)Decode/EXecute stage
+    input  logic        idex_MemRead,
+    input  logic [4:0]  idex_Rt,
+    input  logic [4:0]  idex_Rs,
+
+    // EXecute/MEMory stage
+    input  logic        exmem_RegWrite,
+    input  logic [4:0]  exmem_Rd,
+
+    // MEMory/WriteBack stage
+    input  logic        memwb_RegWrite,
+    input  logic [4:0]  memwb_Rd,
+
+    // (I)Fetch/(I)Decode stage
+    input  logic [4:0]  ifid_Rs,
+    input  logic [4:0]  ifid_Rt,
+
+    // branch / jump control
+    input  logic        branch_taken,
+    input  logic        jump_taken,
+
+    // outputs
+    output logic [1:0]  forwardA,
+    output logic [1:0]  forwardB,
+    output logic        stallF, // Stall OC register
+    output logic        stallD, // Stall Instruction Memory
+    output logic        flushE, // Flush ALU inputs
+    output logic        flushD  // Flush
+);
+
+    // Forwarding encoding:
+    // 00 = no forwarding
+    // 01 = forward from MEM/WB
+    // 10 = forward from EX/MEM
+
+    always_comb begin
+        // defaults
+        forwardA = 2'b00;
+        forwardB = 2'b00;
+        stallF   = 1'b0;
+        stallD   = 1'b0;
+        flushE   = 1'b0;
+        flushD   = 1'b0;
+
+        // Forwarding for ALU src A
+        if (exmem_RegWrite && (exmem_Rd != 5'd0) && (exmem_Rd == idex_Rs))
+            forwardA = 2'b10;
+        else if (memwb_RegWrite && (memwb_Rd != 5'd0) && (memwb_Rd == idex_Rs))
+            forwardA = 2'b01;
+
+        // Forwarding for ALU src B
+        if (exmem_RegWrite && (exmem_Rd != 5'd0) && (exmem_Rd == idex_Rt))
+            forwardB = 2'b10;
+        else if (memwb_RegWrite && (memwb_Rd != 5'd0) && (memwb_Rd == idex_Rt))
+            forwardB = 2'b01;
+
+        // -------------------------
+        // Load-use hazard stall
+        // if instruction in EX is a load and
+        // next instruction uses its result
+        // -------------------------
+        if (idex_MemRead &&
+            ((idex_Rt == ifid_Rs) || (idex_Rt == ifid_Rt))) begin
+            stallF = 1'b1;
+            stallD = 1'b1;
+            flushE = 1'b1;   // insert bubble into EX
+        end
+
+        // -------------------------
+        // Control hazard flush
+        // branch/jump resolved in EX
+        // -------------------------
+        if (branch_taken || jump_taken) begin
+            flushD = 1'b1;   // flush wrong instruction in decode
+            flushE = 1'b1;   // flush wrong instruction in execute
+        end
+    end
+
+endmodule
+`endif
@@ -2,14 +2,17 @@
 `define INSTRUCTION_COUNTER_H

 module instruction_counter #(parameter width=5)(
-    input logic [0:0] clk, input logic [0:0] we,
+    input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] we,
    input logic [2**width-1:0] W,
    output logic [2**width-1:0] addr
 );

    logic [2**width-1:0] pc;
-    always_ff @(posedge clk) begin
-        if (we) begin
+    
+    always_ff @(posedge clk or posedge rst) begin
+        if (rst) begin
+            pc <= {(2**width){1'b0}};
+        end else if (we) begin
            pc <= W;
        end else begin
            pc <= pc + 4;
@@ -0,0 +1,12 @@
+module lu #(width=8) (
+    input logic [1:0] op,
+    input logic [width-1:0] A, input logic [width-1:0] B,
+    output logic [width-1:0] OUT_1);
+
+    always_comb begin
+        if      (op == 2'b00) OUT_1 =   A & B;
+        else if (op == 2'b01) OUT_1 =   A | B;
+        else if (op == 2'b10) OUT_1 =   A ^ B;
+        else if (op == 2'b10) OUT_1 = ~(A | B);
+    end
+endmodule
@@ -1,76 +1,101 @@
 `include "assignment2.sv"

+`timescale 1us/10ns
+
 `define PRINT_REGISTERS(regs)\
    $display("\tt0-t8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n\ts0-s8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n",\
        regs[8], regs[9], regs[10], regs[11], regs[12], regs[13], regs[14], regs[15],   \
        regs[16], regs[17], regs[18], regs[19], regs[20], regs[21], regs[22], regs[23]  \
    );
 `define TEST_CHECK(cond) if (cond) begin end else begin   \
-        $display("Check %s failed\n", `"cond`");          \
+        $display("Check %s failed", `"cond`");            \
        `PRINT_REGISTERS(CPU.REGS.regs);                  \
        num_errors += 1;                                  \
    end

-module mips_tb(input logic [0:0] clk);
-    assignment2 #(5) CPU (clk);
+module mips_tb();
+    logic [0:0] clk;
+    logic [0:0] rst;
+    assignment2 #(5) CPU (clk, rst);
+
+    initial clk = 0;
+    initial rst = 0;
+    always #1 clk = ~clk;

    integer num_errors = 0;
    initial begin
+        rst = 1;
+        #2;
+        rst = 0;
+        #2;
+
+        $dumpfile("output.vcd");
+		$dumpvars(0, clk);
+		$dumpvars(1, CPU.REGS);
+		$dumpvars(2, CPU.ROM);
+		$dumpvars(3, CPU.PC);
+		$dumpvars(4, CPU.pc_addr);
+		$dumpvars(5, CPU.CONTROL_UNIT);
+		$dumpvars(5, CPU.instruction);
+		$dumpvars(5, CPU.ALU);
+		$dumpvars(6, CPU.flags);
+
        // Zero out lower registers
        $display("Beginning MIPS tests");
-        assign num_errors = 0;
-
-        for (integer N = 1; N < 32; ++N)
-            CPU.REGS.regs[N] = 32'd0;

        // Check R-type / initialise
-        #1;
+        #2;
        `TEST_CHECK(CPU.REGS.regs[8] == 32'd0);
-        #1;
+        #2;
        `TEST_CHECK(CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7));

        // Check load-store
-        #1;
+        #2;
        `TEST_CHECK(CPU.RAM.mem[0] == CPU.REGS.regs[9]);
-        #1;
+        #2;
        `TEST_CHECK(CPU.REGS.regs[10] == CPU.RAM.mem[0]);

        // Check arithmetic
-        #1;
+        #2;
        `TEST_CHECK(CPU.REGS.regs[11] == (CPU.REGS.regs[9] + CPU.REGS.regs[10]));
-        #1;
+        #2;
        `TEST_CHECK(CPU.REGS.regs[12] == (CPU.REGS.regs[9] - CPU.REGS.regs[11]));
-        #1;
+        #2;
        `TEST_CHECK(CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3));
-        #1;
+        #2;
        `TEST_CHECK(CPU.REGS.regs[14] == (CPU.REGS.regs[12] + CPU.REGS.regs[13]));

        // Check logic instructions
-        #1;
+        #2;
        `TEST_CHECK(CPU.REGS.regs[16] == (CPU.REGS.regs[9] & CPU.REGS.regs[13]));
-        #1;
+        #2;
        `TEST_CHECK(CPU.REGS.regs[17] == (CPU.REGS.regs[9] | CPU.REGS.regs[13]));
-        #1;
+        #2;
        `TEST_CHECK(CPU.REGS.regs[18] == (CPU.REGS.regs[9] ^ CPU.REGS.regs[13]));
-        #1;
+        #2;
        `TEST_CHECK(CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ));

        // Check SLT instructions
-        #1;
+        #2;
        `TEST_CHECK(CPU.REGS.regs[20] == $signed(CPU.REGS.regs[12]) < $signed(CPU.REGS.regs[14]));
-        #1;
+        #2;
        `TEST_CHECK(CPU.REGS.regs[21] == $unsigned(CPU.REGS.regs[12]) < $unsigned(CPU.REGS.regs[14]));
        
        // Check loop branching
+        #2;
        for (integer N = 1; N < 11; ++N) begin
-            #1;
-            `TEST_CHECK(CPU.REGS.regs[0] == 32'(N));
-            #1;
+            #2;
+            `TEST_CHECK(CPU.REGS.regs[8] == 32'(N));
+            
+            #2;
            `TEST_CHECK(CPU.REGS.regs[22] == $unsigned(CPU.REGS.regs[8]) < $unsigned(CPU.REGS.regs[13]));
+            if (N < 10)
+                #2;
+            #2;
        end

        // Final state check
-        #1;
+        #2;
        `TEST_CHECK(CPU.REGS.regs[8]  == 32'd10);
        `TEST_CHECK(CPU.REGS.regs[9]  == 32'd7);
        `TEST_CHECK(CPU.REGS.regs[10] == 32'd7);
@@ -89,7 +114,10 @@ module mips_tb(input logic [0:0] clk);
        `TEST_CHECK(CPU.REGS.regs[22] == 32'd0);
        `TEST_CHECK(CPU.REGS.regs[23] == 32'd0);

-        if (num_errors == 0) $display("\x1b[38;5;10mAll MIPS tests passing\x1b[m");
-        else $display("\x1b[38;5;9m%0d MIPS test(s) failing\x1b[m", num_errors);
+        if (num_errors == 0) begin $display("\x1b[38;5;10mAll MIPS tests passing\x1b[m");
+        end else begin $display("\x1b[38;5;9m%0d MIPS test(s) failing\x1b[m", num_errors); end
+
+        $dumpflush;
+        $finish;
    end
 endmodule
@@ -2,25 +2,22 @@
 `define RAM_H

 module ram #(addrwidth=9, datawidth=5)(
-    input logic [0:0] clk,
-    input logic [2**addrwidth-1:0] addr,
+    input logic [0:0] clk, input logic [0:0] rst,
+    input logic [addrwidth-1:0] addr,
    input logic [0:0] we,
-    input logic [datawidth-1:0] data_in,
-    output logic [datawidth-1:0] data_out
+    input logic [2**datawidth-1:0] data_in,
+    output logic [2**datawidth-1:0] data_out
 );

    // TODO: Make this byte-sized, NOT word-sized!
-    logic [2**datawidth-1:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0];
-
-    // NOTE: Possible issue with assignments still pending by end of initial block
-    initial begin
-        for (integer ADDR = 0; ADDR < 2**(addrwidth+$clog2(datawidth)-3); ++ADDR) begin
-            mem[ADDR] <= 8'b0;
-        end
-    end
+    logic [2**datawidth-1:0] mem[0:255];

    always_ff @(posedge clk) begin
-        if (we) begin
+        if (rst) begin
+            for (integer ADDR = 0; ADDR < 256; ADDR = ADDR + 1) begin
+                mem[ADDR] <= 32'b0;
+            end
+        end else if (we) begin
            mem[addr] <= data_in;
        end
    end
@@ -12,7 +12,8 @@ module register_file #(parameter width=5, parameter nregs=5)(
    logic [2**width-1:0] regs[2**nregs];

    initial begin
-        regs[0] = {(2**width){1'b0}};
+        for (integer N = 0; N < (2**nregs); ++N)
+            regs[N] = 32'd0;
    end

    always_ff @(posedge clk) begin
@@ -3,19 +3,19 @@

 module rom #(parameter m=7,p=4) (
        input logic [m-1:0] Ad,
-        output logic [p-1:0] Dout
+        output logic [2**p-1:0] Dout
    );
    
-    logic [p-1:0] mem[2**m-1:0];
-    assign Dout = mem[Ad];
+    logic [2**p-1:0] mem[2**m];
+    assign Dout = mem[Ad>>2];   // Because word-size versus byte size hack

    //Load the program in memory
    // The machine code stored in text file program.dat written in Hex format
    initial begin
        `ifdef QUARTUS_SYNTH
-            $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
+            $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
        `else
-            $readmemh("../asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
+            $readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
        `endif
    end
 endmodule // end rom module
@@ -3,19 +3,19 @@

 module rom #(parameter m=7,p=4) (
        input logic [m-1:0] Ad,
-        output logic [p-1:0] Dout
+        output logic [2**p-1:0] Dout
    );
    
-    logic [p-1:0] mem[2**m-1:0];
-    assign Dout = mem[Ad];
+    logic [2**p-1:0] mem[2**m];
+    assign Dout = mem[Ad>>2];   // Because word-size versus byte size hack

    //Load the program in memory
    // The machine code stored in text file program.dat written in Hex format
    initial begin
        `ifdef QUARTUS_SYNTH
-            $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
+            $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
        `else
-            $readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
+            $readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
        `endif
    end
 endmodule // end rom module
@@ -13,28 +13,28 @@ module seven_seg_4digit (
    // Rightmost digit
    seven_seg digit0 (
        .num(num[3:0]),
-        .rbi_inv(1'b0),
+        .rbi_inv(1'b1),
        .segments(segments0)
    );

    // Second digit from right
    seven_seg digit1 (
        .num(num[7:4]),
-        .rbi_inv(1'b0),
+        .rbi_inv(1'b1),
        .segments(segments1)
    );

    // Third digit from right
    seven_seg digit2 (
        .num(num[11:8]),
-        .rbi_inv(1'b0),
+        .rbi_inv(1'b1),
        .segments(segments2)
    );

    // Leftmost digit
    seven_seg digit3 (
        .num(num[15:12]),
-        .rbi_inv(1'b0),
+        .rbi_inv(1'b1),
        .segments(segments3)
    );

@@ -0,0 +1,19 @@
+`ifndef SHIFTER_H_SV
+`define SHIFTER_H_SV
+module shifter #(width=8)(input logic [2:0] op,
+    input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B,
+    output logic[width-1:0] OUT_1);
+
+    always_comb begin
+        case (op)
+            3'b000: OUT_1 = A << C;
+            3'b001: OUT_1 = A >> C;
+            3'b011: OUT_1 = $signed(A) >>> C;
+            3'b100: OUT_1 = A << B;
+            3'b101: OUT_1 = A >> B;
+            3'b111: OUT_1 = $signed(A) >>> B;
+            default:OUT_1 = A;
+        endcase
+    end    
+endmodule
+`endif
@@ -6,12 +6,11 @@ module sign_extender #(in_width=4, out_width=5)(
    input logic [2**in_width-1:0] val,
    output logic [2**out_width-1:0] ext_val
 );
-    always_comb begin
-        if (op) begin
-            ext_val = { {(2**(out_width-in_width)){val[2**in_width-1]}}, val};
-        end else begin
-            ext_val = ({{(2**(out_width-in_width)){1'b0}}, val});
-        end
-    end
+    logic [0:0] msb;
+    assign msb = (val >> (in_width-1)) & 1'b1;
+    assign ext_val = op
+        ? { {(2**out_width - 2**in_width){msb}}, val }
+        : { {(2**out_width - 2**in_width){1'b0}}, val };
+  
 endmodule
 `endif
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-!s107 /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv|
-!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv|
-!i113 1
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 R0
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-!s100 FhA1A;hJHXYBBj3k;<@TW0
+!s100 TM=bHR22b5BF7BGjf7QYh2
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-I7[zSLUT47VibC4BZ`m8FC1
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-w1792035553
-8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
-F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
-!i122 92
-L0 4 24
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+8register_file.sv
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-!s107 /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv|
-!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv|
-!i113 1
+R7
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+!i113 1
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 vrom
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-R1
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 !i10b 1
-!s100 WU3`[b3K8gX:gOXzLkih[1
+!s100 zLh]ZiD;FcdhG3I]1fk3P2
 R2
-INYZO14fR4zIzAHU<HO=jM1
+I8o3_6E:`aQh^;J7VVYZIJ2
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-w1792107144
-8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv
-F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv
-!i122 93
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+8rom.sv
+From.sv
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-R5
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 r1
 !s85 0
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-R16
-!s107 /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv|
-!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv|
+R19
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 !i113 1
-R9
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 vseven_seg
 R0
-R1
+Z25 !s110 1793848696
 !i10b 1
 !s100 ^3LXNA>i`]oD>7BNB:Rd?3
 R2
@@ -420,49 +495,49 @@ IedFU7?nB5ZOibY?bC8=L41
 R3
 S1
 R4
-R14
+R23
 8seven_seg.sv
 Fseven_seg.sv
-!i122 96
+!i122 207
 L0 3 23
-R5
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 r1
 !s85 0
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-R16
-Z17 !s107 seven_seg.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv|
-Z18 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv|
+Z26 !s108 1793848696.000000
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+Z28 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv|
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-!s100 MRn_YTIW^S4cR39n=0RMi0
+!s100 kl;BlN=e=UfChCC`DZJA01
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-!i122 95
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-R5
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 !s107 seven_seg.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv|
 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv|
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@@ -473,18 +548,18 @@ R4
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 !i113 1
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@@ -495,24 +570,24 @@ IzJzhQo`olGLa0f4lM55A42
 R3
 S1
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-R14
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-!i122 98
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 !s85 0
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-Z19 !s107 shifter.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv|
-Z20 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv|
-!i113 1
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 R9
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 R0
-R1
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 !i10b 1
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@@ -520,43 +595,43 @@ Ia6ohf92lD=P<P]lDi667i2
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 R4
-R13
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 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv
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-R9
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-!s100 aKV[]M4PV<7m9ohWC7JSA0
+!s100 dXL[XDH1LfSe`PJjMiOTD2
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-w1792038654
-8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
-F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
-!i122 99
-L0 4 13
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+w1792644107
+8sign_extender.sv
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-!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv|
-!i113 1
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@@ -121,4 +121,10 @@ set_location_assignment PIN_AC24 -to out_seg_3[5]
 set_location_assignment PIN_AC23 -to out_seg_3[6]


+set_location_assignment PIN_AC9 -to rst[0]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to rst[0]
+set_location_assignment PIN_F7 -to out_seg_0[0]
+set_location_assignment PIN_F6 -to out_seg_1[0]
+set_location_assignment PIN_G6 -to out_seg_2[0]
+set_location_assignment PIN_G7 -to out_seg_3[0]
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
Author	SHA1	Message	Date
TroubleElectrical	d2ba06b255	Added Hazard Unit file (tested compiling correctly) labelled variables inside off of the Assignment 3 Questions PDF Figure 2. Also have a placeholder MUX to place before the ALU for adding hazard unit functionality	2026-11-08 12:32:40 +11:00
riley	fe53955748	Fixed bug in test code where there was a hazzard, despite testing assuming no hazzard. Updated testbench to reflect this (Ln57-62). Added mem[0x000] to log message when printing registers. Replaced 8 delay with explicit 5x 2 delays. (NOTE: Needed an extra one for ensuring write-back when comparing results. Fixed bug where the wrong registers were being added together when creating the comparison point in the testbench. Fixed testbench bug where S4 was checked twice and S5 not checked at all. Updated display message on test failure to reflect that it is the pipelined version, not the single-cycle.	2026-11-05 16:15:06 +11:00
riley	de1f346f64	Updated assignment3 instruction counter code to be more consistent with other modules	2026-11-05 15:46:05 +11:00
TroubleElectrical	c894488c44	Fixed ByteIM.sv and removed seven seg from A3 code	2026-11-05 14:33:41 +11:00
riley	74a15cf038	Made ROM binary file configurable via a parameter. Updated assignment2 and assignment3 to reflect this. Added bit slicing in assignment2 for ram/rom addresses.	2026-11-05 14:27:01 +11:00
TroubleElectrical	00b2087860	Added project to modelsim	2026-11-05 14:25:34 +11:00
riley	38fa35fccd	Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module	2026-11-05 14:10:13 +11:00
riley	cc98bfbf02	Fixed compile error caused by trailing comma	2026-11-05 12:25:01 +11:00
riley	f8ea90e41d	Created assignment 3 MIPS module that uses pipelining	2026-11-04 17:28:36 +11:00
riley	704286f0e6	Renamed MIPS test to be a single cycle test	2026-11-04 15:42:52 +11:00
riley	ef6bd3aec9	Added test assemblies for assignment 3 / pipelining	2026-11-04 15:42:22 +11:00
riley	8f9ec010ac	Updated gate register module to support arbitary delays to prevent littering uper-level code with gatereg->gatereg logic values.	2026-11-04 15:40:25 +11:00
riley	b046ad7db0	Created register for gating pipeline stage results	2026-10-29 15:34:31 +11:00
TroubleElectrical	8b48084fa5	Repaired Sign extender module again to ensure only combinational logic used (There was a compilation error before, also compiled and tested code on board)	2026-10-22 15:53:15 +11:00
riley	973b9260b6	Fixed (maybe bug) in demo program where program branches back to prior instruction.	2026-10-20 16:21:55 +11:00
riley	5eb78e92e9	Fixed bugs in sign extender	2026-10-20 16:14:02 +11:00
riley	b52f01c3be	Added some delay to better test final branch/halt.	2026-10-20 16:02:40 +11:00
riley	9648db6e77	Switched to used boolean `&&` rather than bitwise `&` in sign extender	2026-10-20 16:02:14 +11:00
riley	a647305bd9	Fixed bug where ram datawidth was not 2^N.	2026-10-20 16:01:34 +11:00
TroubleElectrical	fb97155731	Added Assignment 2 submission zip file	2026-10-16 15:09:48 +11:00
TroubleElectrical	d962a1b557	Added code to display current PC, Removed Blanking from 7seg 4 digits, Changed reset to a switch rather than button Compiled working version for board	2026-10-16 14:27:29 +11:00
TroubleElectrical	91a5090528	Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)	2026-10-16 12:59:50 +11:00
riley	2f652705cc	Fixed timing in testbench for branch iteration.	2026-10-16 12:51:21 +11:00
riley	59f7f372f6	Fixed bug where ASU intermediate was being treated as the overflow flag rather than an intermediate.	2026-10-16 12:33:04 +11:00
riley	e7fff9f3dc	Added explicit rst input to RAM and PC as well as the MIPS processor.	2026-10-16 12:11:19 +11:00
riley	c717bf189c	Added comment to document the zero-flag	2026-10-16 11:57:55 +11:00
riley	5ae9125e06	Fixed a couple bugs introduced from merge-conflict resolution	2026-10-16 11:50:07 +11:00
riley	8a682347f0	Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni	2026-10-16 11:44:03 +11:00
riley	559ff01d69	Fixed printing annoyance. Added variable dumping to a wavefile. Updated delay to 2 units (as there is 1 unit of clk being high and 1 unit low). Removed register initialisation code from testbench. Fixed typo when wanting to check T0 (R8) but was checking R0. Added explicit if-else begin-end blocks to logging and a simulation exit when the testbench is done.	2026-10-16 11:41:33 +11:00
riley	92a0cb17da	Updated assignment 2 to reflect prior changes. Fixed instruction ordering for register file module (again). Fixed typo that limited the space the ALU could write its flags out to. Swapped ordering to be correct when determining if we are storing the result from ALU or MEM. Added a QUARTUS_SYNTH around the display logic at the end of the module. Partially fixed control_unit module, still seems to need some changes as branching doesn't appear to work at all.	2026-10-16 11:38:35 +11:00
riley	65be2c2d61	Made sign extension explicit to remove bit indexing (which iverilog doesn't like) and a tad more readable.	2026-10-16 11:35:24 +11:00
riley	878f949e5f	Made addrwidth sizing consistent with the 2^N used everywhere	2026-10-16 11:34:31 +11:00
riley	0ea3e0fa12	Added initialisation blocks for PC and GPR's	2026-10-16 11:33:45 +11:00
riley	12ae58ad86	Removed flag assignment from within ALU OP case statement and instead perform it at the end. Made bit index for the ASU OP more explicit.	2026-10-16 11:32:24 +11:00
riley	4c7e2ff085	Fixed instruction width issue in ROM. Stripped all comments to form minimal HEX file to rule out possible parser issues.	2026-10-16 11:29:04 +11:00