10 Commits

Include renames

Author	SHA1	Message	Date
TroubleElectrical	00b2087860	Added project to modelsim	2026-11-05 14:25:34 +11:00
TroubleElectrical	91a5090528	Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)	2026-10-16 12:59:50 +11:00
TroubleElectrical	5d9e7f541e	Updated RAM code to make sure Bus width is 32 bits	2026-10-16 11:32:47 +11:00
TroubleElectrical	dca673b039	Added files into modelsim folder	2026-10-16 10:10:37 +11:00
TroubleElectrical	00167dabc8	Updated ModelSim Files	2026-09-16 10:15:08 +10:00
TroubleElectrical	9e5fb6f52b	Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board	2026-09-15 16:52:48 +10:00
TroubleElectrical	05361dcf70	Added all Testbenches to Modelsim and confirmed working operation	2026-09-15 15:15:00 +10:00
TroubleElectrical	a73990b242	Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2)	2026-09-10 15:24:44 +10:00
TroubleElectrical	dc32347c9b	Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)	2026-09-09 14:27:11 +10:00
TroubleElectrical	60e5dae43b	Added ModelSim folder (and have to add files into it as to allow for different testbench code)	2026-09-08 16:32:01 +10:00