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00b2087860688d33b6e5bf22e5510266c3c72b40
FPGA_Uni/ModelSim
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History
TroubleElectrical 00b2087860 Added project to modelsim
2026-11-05 14:25:34 +11:00
..
work
Added project to modelsim
2026-11-05 14:25:34 +11:00
alu_tb.sv
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
alu.sv
Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)
2026-10-16 12:59:50 +11:00
alu.sv.bak
Added project to modelsim
2026-11-05 14:25:34 +11:00
assignment2.sv
Added project to modelsim
2026-11-05 14:25:34 +11:00
assignment2.sv.bak
Added project to modelsim
2026-11-05 14:25:34 +11:00
assignment3.sv
Added project to modelsim
2026-11-05 14:25:34 +11:00
assignment3.sv.bak
Added project to modelsim
2026-11-05 14:25:34 +11:00
Assignment_1_Q1.cr.mti
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
Assignment_1_Q1.mpf
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
Assignment_1_Q2.cr.mti
Updated RAM code to make sure Bus width is 32 bits
2026-10-16 11:32:47 +11:00
Assignment_1_Q2.mpf
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
Assignment_1_Q3.cr.mti
Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2)
2026-09-10 15:24:44 +10:00
Assignment_1_Q3.mpf
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
Assignment_1_Q4.cr.mti
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
Assignment_1_Q4.mpf
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
Assignment_1_Q5.cr.mti
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
Assignment_1_Q5.mpf
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
Assignment_1_Q6.cr.mti
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
Assignment_1_Q6.mpf
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
Assignment_2.cr.mti
Added project to modelsim
2026-11-05 14:25:34 +11:00
Assignment_2.mpf
Added project to modelsim
2026-11-05 14:25:34 +11:00
asu_tb.sv
Updated ModelSim Files
2026-09-16 10:15:08 +10:00
asu_tb.sv.bak
Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2)
2026-09-10 15:24:44 +10:00
asu.sv
Added files into modelsim folder
2026-10-16 10:10:37 +11:00
asu.sv.bak
Added project to modelsim
2026-11-05 14:25:34 +11:00
ByteIM.sv
Updated RAM code to make sure Bus width is 32 bits
2026-10-16 11:32:47 +11:00
ByteIM.sv.bak
Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)
2026-10-16 12:59:50 +11:00
control_unit.sv
Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)
2026-10-16 12:59:50 +11:00
gatereg.sv
Added project to modelsim
2026-11-05 14:25:34 +11:00
instruction_classifier_tb.sv
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
instruction_classifier.sv
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
instruction_counter.sv
Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)
2026-10-16 12:59:50 +11:00
lu_tb.sv
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
lu.sv
Added files into modelsim folder
2026-10-16 10:10:37 +11:00
lu.sv.bak
Added project to modelsim
2026-11-05 14:25:34 +11:00
mips.sv
Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)
2026-10-16 12:59:50 +11:00
ram.sv
Added project to modelsim
2026-11-05 14:25:34 +11:00
register_file.sv
Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)
2026-10-16 12:59:50 +11:00
rom.sv
Added project to modelsim
2026-11-05 14:25:34 +11:00
rom.sv.bak
Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)
2026-10-16 12:59:50 +11:00
seven_seg_4digit.sv
Added project to modelsim
2026-11-05 14:25:34 +11:00
seven_seg_tb.sv
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
seven_seg.sv
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
shifter_tb.sv
Updated ModelSim Files
2026-09-16 10:15:08 +10:00
shifter.sv
Added files into modelsim folder
2026-10-16 10:10:37 +11:00
shifter.sv.bak
Added project to modelsim
2026-11-05 14:25:34 +11:00
sign_extender.sv
Added project to modelsim
2026-11-05 14:25:34 +11:00
tests.sv
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
transcript
Added project to modelsim
2026-11-05 14:25:34 +11:00
vsim.wlf
Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)
2026-10-16 12:59:50 +11:00