TroubleElectrical/FPGA_Uni
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Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)

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TroubleElectrical committed 2026-09-09 14:27:11 +10:00
1 parent 5acf1c8b87
commit dc32347c9b
212 files changed
+8657 -71
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ModelSim/Assignment_1_Q2.cr.mti
+15
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@@ -1 +1,16 @@
/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module lu
Top level modules:
lu
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module lu
-- Compiling module lu_tb
Top level modules:
lu_tb
} {} {}}
ModelSim/Assignment_1_Q2.mpf
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@@ -412,9 +412,9 @@ Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 2
Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv
Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1788845636 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1788845636 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1788848626 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788926090 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
ModelSim/lu_tb.sv
+20 -19
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@@ -1,36 +1,36 @@
`include "lu.sv"
module lu_tb #(W=4)();
module lu_tb #(parameter W=4)();
logic [1:0] op;
logic [W-1:0] A;
logic [W-1:0] B;
logic [W-1:0] C;
logic [W-1:0] C_exp[16];
lu #(W) dut();
lu #(W/2) dut(op, A, B, C);
integer error_count;
initial begin
// AND
C_exp[0] = {W{1'b0}};
C_exp[1] = {W{1'b0}};
C_exp[2] = {W{1'b0}};
C_exp[3] = {W{1'b0}};
C_exp[0] = {{W{1'b0}}, {1'b0}};
C_exp[1] = {{W{1'b0}}, {1'b0}};
C_exp[2] = {{W{1'b0}}, {1'b0}};
C_exp[3] = {{W{1'b0}}, {1'b1}};
// OR
C_exp[4] = {W{1'b0}};
C_exp[5] = {W{1'b1}};
C_exp[6] = {W{1'b1}};
C_exp[7] = {W{1'b1}};
C_exp[4] = {{W{1'b0}}, {1'b0}};
C_exp[5] = {{W{1'b0}}, {1'b1}};
C_exp[6] = {{W{1'b0}}, {1'b1}};
C_exp[7] = {{W{1'b0}}, {1'b1}};
// XOR
C_exp[8] = {W{1'b0}};
C_exp[9] = {W{1'b1}};
C_exp[10] = {W{1'b1}};
C_exp[11] = {W{1'b0}};
C_exp[8] = {{W{1'b0}}, {1'b0}};
C_exp[9] = {{W{1'b0}}, {1'b1}};
C_exp[10] = {{W{1'b0}}, {1'b1}};
C_exp[11] = {{W{1'b0}}, {1'b0}};
// NOR
C_exp[12] = {W{1'b1}};
C_exp[13] = {W{1'b0}};
C_exp[14] = {W{1'b0}};
C_exp[15] = {W{1'b0}};
C_exp[12] = {{W{1'b1}}, {1'b1}};
C_exp[13] = {{W{1'b1}}, {1'b0}};
C_exp[14] = {{W{1'b1}}, {1'b0}};
C_exp[15] = {{W{1'b1}}, {1'b0}};
error_count = 0;
op = 0;
@@ -42,12 +42,13 @@ module lu_tb #(W=4)();
for (integer K = 0; K < 2; ++K) begin
#1;
if (C != C_exp[N*2*2 + M*2 + K]) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", op, A, B, C, C_exp[N*2*2 + M*2 + K]);
$display("\t\x1b[38;5;9mLU(%0d) Op 0b%b(0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", N*2*2+M*2+K, op, A, B, C, C_exp[N*2*2 + M*2 + K]);
error_count = error_count + 1;
end
B = 1;
end
A = 1;
B = 0;
end
A = 0;
B = 0;
ModelSim/transcript
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@@ -1,46 +1,19 @@
# Loading project Assignment_1_Q2
# Compile of lu.sv was successful.
# Compile of lu_tb.sv failed with 1 errors.
# 2 compiles, 1 failed with 1 error.
# Compile of lu_tb.sv failed with 1 errors.
# Compile of lu.sv was successful.
# Compile of lu_tb.sv was successful.
# 2 compiles, 0 failed with no errors.
vsim work.lu_tb
# vsim work.lu_tb
# Start time: 16:26:37 on Sep 08,2026
# Start time: 13:56:39 on Sep 09,2026
# Loading sv_std.std
# Loading work.lu_tb
# Loading work.lu
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'dut'. Expected 4, found 0.
# Time: 0 ps Iteration: 0 Instance: /lu_tb/dut File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv Line: 10
# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'op'.
# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'A'.
# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'B'.
# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'Y'.
add wave -position end sim:/lu_tb/op
add wave -position end sim:/lu_tb/A
add wave -position end sim:/lu_tb/A
add wave -position end sim:/lu_tb/B
add wave -position end sim:/lu_tb/C
restart -f
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
quit -sim
# End time: 16:28:07 on Sep 08,2026, Elapsed time: 0:01:30
# Errors: 0, Warnings: 12
# Compile of lu.sv was successful.
# Compile of lu_tb.sv was successful.
# 2 compiles, 0 failed with no errors.
vsim work.lu_tb
# vsim work.lu_tb
# Start time: 16:30:51 on Sep 08,2026
# Loading sv_std.std
# Loading work.lu_tb
# Loading work.lu
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'dut'. Expected 4, found 0.
# Time: 0 ps Iteration: 0 Instance: /lu_tb/dut File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv Line: 10
# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'op'.
# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'A'.
# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'B'.
# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'Y'.
quit -sim
# End time: 16:31:17 on Sep 08,2026, Elapsed time: 0:00:26
# Errors: 0, Warnings: 7
# End time: 13:59:50 on Sep 09,2026, Elapsed time: 0:03:11
# Errors: 0, Warnings: 1
ModelSim/vsim.wlf
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ModelSim/work/_info
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@@ -11,7 +11,7 @@ cModel Technology
d/home/oliver/intelFPGA/20.1/modelsim_ase/bin
vlu
Z0 DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3
Z1 !s110 1788849038
Z1 !s110 1788926178
!i10b 1
!s100 nmDP9zlMCJDa@W3_FY5m[2
Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1
@@ -22,13 +22,13 @@ Z4 d/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim
w1788845636
8lu.sv
Flu.sv
!i122 6
!i122 8
L0 1 16
Z5 OV;L;2020.1;71
r1
!s85 0
31
Z6 !s108 1788849037.000000
Z6 !s108 1788926178.000000
!s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
Z7 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
!i113 1
@@ -38,17 +38,17 @@ vlu_tb
R0
R1
!i10b 1
!s100 gdCQZUG[6;:5f<I_jIOd?1
!s100 AE_liX6DCD[3>b;K6Wgf72
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!i122 6
L0 3 57
!i122 8
L0 3 58
R5
r1
!s85 0
ModelSim/work/_lib.qdb
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