TroubleElectrical 00167dabc8 Updated ModelSim Files

2026-09-16 10:15:08 +10:00

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work

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

alu_tb.sv

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

alu.sv

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

Assignment_1_Q1.cr.mti

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

Assignment_1_Q1.mpf

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

Assignment_1_Q2.cr.mti

Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)

2026-09-09 14:27:11 +10:00

Assignment_1_Q2.mpf

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

Assignment_1_Q3.cr.mti

Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2)

2026-09-10 15:24:44 +10:00

Assignment_1_Q3.mpf

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

Assignment_1_Q4.cr.mti

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

Assignment_1_Q4.mpf

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

Assignment_1_Q5.cr.mti

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

Assignment_1_Q5.mpf

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

Assignment_1_Q6.cr.mti

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

Assignment_1_Q6.mpf

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

asu_tb.sv

Updated ModelSim Files

2026-09-16 10:15:08 +10:00

asu_tb.sv.bak

Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2)

2026-09-10 15:24:44 +10:00

asu.sv

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

instruction_classifier_tb.sv

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

instruction_classifier.sv

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

lu_tb.sv

Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)

2026-09-09 14:27:11 +10:00

lu.sv

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

seven_seg_tb.sv

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

seven_seg.sv

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

shifter_tb.sv

Updated ModelSim Files

2026-09-16 10:15:08 +10:00

shifter.sv

Updated ModelSim Files

2026-09-16 10:15:08 +10:00

tests.sv

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

transcript

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

vsim.wlf

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00