Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
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@@ -220,7 +220,7 @@ Resolution = ps
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UserTimeUnit = default
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; Default run length
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RunLength = 100 ps
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RunLength = 0 ps
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; Maximum iterations that can be run without advancing simulation time
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IterationLimit = 5000
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@@ -412,9 +412,9 @@ Project_DefaultLib = work
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Project_SortMethod = unused
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Project_Files_Count = 2
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Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv
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Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
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Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_Sim_Count = 0
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Project_Folder_Count = 0
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Echo_Compile_Output = 0
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+8
-128
@@ -1,131 +1,7 @@
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# Loading project Assignment_1_Q3
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# Compile of asu.sv was successful.
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# Compile of asu_tb.sv was successful.
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# 2 compiles, 0 failed with no errors.
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vsim work.asu_tb
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# vsim work.asu_tb
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# Start time: 15:01:26 on Sep 15,2026
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# Loading sv_std.std
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# Loading work.asu_tb
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# Loading work.asu
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add wave -position end sim:/asu_tb/op
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add wave -position end sim:/asu_tb/A
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add wave -position end sim:/asu_tb/B
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add wave -position end sim:/asu_tb/C
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add wave -position end sim:/asu_tb/Cout
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add wave -position end sim:/asu_tb/Cin
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run
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# Beginning ASU tests
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# [38;5;10mAll ASU tests passing[m
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quit -sim
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# End time: 15:03:03 on Sep 15,2026, Elapsed time: 0:01:37
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# Errors: 0, Warnings: 2
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# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini
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# Loading project Assignment_1_Q4
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# Compile of alu.sv was successful.
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# Compile of alu_tb.sv was successful.
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# 2 compiles, 0 failed with no errors.
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vsim work.alu_tb
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# vsim work.alu_tb
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# Start time: 15:04:11 on Sep 15,2026
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# Loading sv_std.std
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# Loading work.alu_tb
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# Loading work.alu
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# Loading work.asu
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# Loading work.lu
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add wave -position end sim:/alu_tb/op_in
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add wave -position end sim:/alu_tb/A_in
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add wave -position end sim:/alu_tb/B_in
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add wave -position end sim:/alu_tb/Y_out
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add wave -position end sim:/alu_tb/flags_out
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add wave -position end sim:/alu_tb/ops
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run
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# Beginning ALU tests
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# [38;5;10mAll ALU tests passing[m
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add wave -position end sim:/alu_tb/error_count
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run
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quit -sim
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# End time: 15:05:53 on Sep 15,2026, Elapsed time: 0:01:42
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# Errors: 0, Warnings: 5
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# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini
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# Loading project Assignment_1_Q5
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# Compile of shifter.sv was successful.
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# Compile of shifter_tb.sv was successful.
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# 2 compiles, 0 failed with no errors.
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vsim work.shifter_tb
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# vsim work.shifter_tb
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# Start time: 15:06:46 on Sep 15,2026
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# Loading sv_std.std
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# Loading work.shifter_tb
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# Loading work.shifter
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add wave -position end sim:/shifter_tb/op
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add wave -position end sim:/shifter_tb/Y
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add wave -position end sim:/shifter_tb/A_in
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add wave -position end sim:/shifter_tb/B_in
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add wave -position end sim:/shifter_tb/C_in
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add wave -position end sim:/shifter_tb/A
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add wave -position end sim:/shifter_tb/B
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add wave -position end sim:/shifter_tb/C
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add wave -position end sim:/shifter_tb/Y
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add wave -position end sim:/shifter_tb/op
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run
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# Beginning Shifter tests
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# [38;5;10mAll Shifter tests passing[m
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quit -sim
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# End time: 15:07:54 on Sep 15,2026, Elapsed time: 0:01:08
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# Errors: 0, Warnings: 5
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# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini
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# Loading project Assignment_1_Q6
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# Compile of instruction_classifier.sv was successful.
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# Compile of instruction_classifier_tb.sv was successful.
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# 2 compiles, 0 failed with no errors.
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vsim work.instruction_classifier_tb
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# vsim work.instruction_classifier_tb
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# Start time: 15:08:34 on Sep 15,2026
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# Loading sv_std.std
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# Loading work.instruction_classifier_tb
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# Loading work.instruction_classifier
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add wave -position end sim:/instruction_classifier_tb/op
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add wave -position end sim:/instruction_classifier_tb/C
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add wave -position end sim:/instruction_classifier_tb/ops
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run
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# Beginning Instruction Classifier tests
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# [38;5;10mAll Instruction Classifier tests passing[m
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quit -sim
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# End time: 15:09:45 on Sep 15,2026, Elapsed time: 0:01:11
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# Errors: 0, Warnings: 5
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# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini
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# Loading project Assignment_1_Q1
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# Compile of seven_seg.sv was successful.
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# Compile of seven_seg_tb.sv was successful.
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# 2 compiles, 0 failed with no errors.
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vsim work.seven_seg_tb
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# vsim work.seven_seg_tb
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# Start time: 15:10:28 on Sep 15,2026
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# Loading sv_std.std
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# Loading work.seven_seg_tb
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# Loading work.seven_seg
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add wave -position end sim:/seven_seg_tb/in_rbi_inv
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add wave -position end sim:/seven_seg_tb/out_segments
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add wave -position end sim:/seven_seg_tb/true_segments
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add wave -position end sim:/seven_seg_tb/N
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add wave -position end sim:/seven_seg_tb/i
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add wave -position 1 sim:/seven_seg_tb/in_num
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run
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# Beginning seven-segment tests
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# [38;5;10mAll seven-segment tests passing[m
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quit -sim
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# End time: 15:12:28 on Sep 15,2026, Elapsed time: 0:02:00
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# Errors: 0, Warnings: 5
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project open /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/Assignment_1_Q2
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# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini
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# Loading project Assignment_1_Q2
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# Compile of lu.sv was successful.
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# Compile of lu_tb.sv was successful.
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# 2 compiles, 0 failed with no errors.
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vsim work.lu_tb
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# vsim work.lu_tb
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# Start time: 15:13:40 on Sep 15,2026
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# Start time: 16:47:26 on Sep 15,2026
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# Loading sv_std.std
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# Loading work.lu_tb
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# Loading work.lu
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@@ -133,9 +9,13 @@ add wave -position end sim:/lu_tb/op
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add wave -position end sim:/lu_tb/A
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add wave -position end sim:/lu_tb/B
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add wave -position end sim:/lu_tb/C
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add wave -position end sim:/lu_tb/C_exp
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run
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# Beginning LU tests
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run
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run
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run
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run -all
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# [38;5;10mAll LU tests passing[m
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quit -sim
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# End time: 15:14:33 on Sep 15,2026, Elapsed time: 0:00:53
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# Errors: 0, Warnings: 3
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# End time: 16:52:34 on Sep 15,2026, Elapsed time: 0:05:08
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# Errors: 0, Warnings: 1
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