This website requires JavaScript.
Explore
Help
Sign In
TroubleElectrical
/
FPGA_Uni
Watch
1
Star
0
Fork
0
Code
Issues
1
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
Files
dc32347c9b23ecd30b4ad1f88e3e187c82953403
FPGA_Uni
/
ModelSim
T
History
TroubleElectrical
dc32347c9b
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
..
work
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
Assignment_1_Q2.cr.mti
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
Assignment_1_Q2.mpf
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
lu_tb.sv
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
lu.sv
Added ModelSim folder (and have to add files into it as to allow for different testbench code)
2026-09-08 16:32:01 +10:00
transcript
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
vsim.wlf
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
