TroubleElectrical/FPGA_Uni
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Author SHA1 Message Date
riley cc98bfbf02 Fixed compile error caused by trailing comma 2026-11-05 12:25:01 +11:00
riley f8ea90e41d Created assignment 3 MIPS module that uses pipelining 2026-11-04 17:28:36 +11:00
riley 704286f0e6 Renamed MIPS test to be a single cycle test 2026-11-04 15:42:52 +11:00
riley ef6bd3aec9 Added test assemblies for assignment 3 / pipelining 2026-11-04 15:42:22 +11:00
riley 8f9ec010ac Updated gate register module to support arbitary delays to prevent littering uper-level code with gatereg->gatereg logic values. 2026-11-04 15:40:25 +11:00
riley b046ad7db0 Created register for gating pipeline stage results 2026-10-29 15:34:31 +11:00
TroubleElectrical 8b48084fa5 Repaired Sign extender module again to ensure only combinational logic used 
(There was a compilation error before, also compiled and tested code on board)
 2026-10-22 15:53:15 +11:00
riley 973b9260b6 Fixed (maybe bug) in demo program where program branches back to prior instruction. 2026-10-20 16:21:55 +11:00
riley 5eb78e92e9 Fixed bugs in sign extender 2026-10-20 16:14:02 +11:00
riley b52f01c3be Added some delay to better test final branch/halt. 2026-10-20 16:02:40 +11:00
riley 9648db6e77 Switched to used boolean && rather than bitwise & in sign extender 2026-10-20 16:02:14 +11:00
riley a647305bd9 Fixed bug where ram datawidth was not 2^N. 2026-10-20 16:01:34 +11:00
TroubleElectrical fb97155731 Added Assignment 2 submission zip file 2026-10-16 15:09:48 +11:00
TroubleElectrical d962a1b557 Added code to display current PC, 
Removed Blanking from 7seg 4 digits,
Changed reset to a switch rather than button
Compiled working version for board
 2026-10-16 14:27:29 +11:00
TroubleElectrical 91a5090528 Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path) 2026-10-16 12:59:50 +11:00
riley 2f652705cc Fixed timing in testbench for branch iteration. 2026-10-16 12:51:21 +11:00
riley 59f7f372f6 Fixed bug where ASU intermediate was being treated as the overflow flag rather than an intermediate. 2026-10-16 12:33:04 +11:00
riley e7fff9f3dc Added explicit rst input to RAM and PC as well as the MIPS processor. 2026-10-16 12:11:19 +11:00
riley c717bf189c Added comment to document the zero-flag 2026-10-16 11:57:55 +11:00
riley 5ae9125e06 Fixed a couple bugs introduced from merge-conflict resolution 2026-10-16 11:50:07 +11:00
riley 8a682347f0 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-16 11:44:03 +11:00
riley 559ff01d69 Fixed printing annoyance. Added variable dumping to a wavefile. Updated delay to 2 units (as there is 1 unit of clk being high and 1 unit low). 
Removed register initialisation code from testbench.
Fixed typo when wanting to check T0 (R8) but was checking R0.
Added explicit if-else begin-end blocks to logging and a simulation exit when the testbench is done.
 2026-10-16 11:41:33 +11:00
riley 92a0cb17da Updated assignment 2 to reflect prior changes. Fixed instruction ordering for register file module (again). Fixed typo that limited the space the ALU could write its flags out to. Swapped ordering to be correct when determining if we are storing the result from ALU or MEM. 
Added a QUARTUS_SYNTH around the display logic at the end of the module.
Partially fixed control_unit module, still seems to need some changes as branching doesn't appear to work at all.
 2026-10-16 11:38:35 +11:00
riley 65be2c2d61 Made sign extension explicit to remove bit indexing (which iverilog doesn't like) and a tad more readable. 2026-10-16 11:35:24 +11:00
riley 878f949e5f Made addrwidth sizing consistent with the 2^N used everywhere 2026-10-16 11:34:31 +11:00
riley 0ea3e0fa12 Added initialisation blocks for PC and GPR's 2026-10-16 11:33:45 +11:00
TroubleElectrical 5d9e7f541e Updated RAM code to make sure Bus width is 32 bits 2026-10-16 11:32:47 +11:00
riley 12ae58ad86 Removed flag assignment from within ALU OP case statement and instead perform it at the end. Made bit index for the ASU OP more explicit. 2026-10-16 11:32:24 +11:00
riley 4c7e2ff085 Fixed instruction width issue in ROM. Stripped all comments to form minimal HEX file to rule out possible parser issues. 2026-10-16 11:29:04 +11:00
TroubleElectrical dca673b039 Added files into modelsim folder 2026-10-16 10:10:37 +11:00
riley 8ed06d38e1 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-16 03:55:57 +11:00
riley 103aa769fd Added testbench for MIPS processor 2026-10-16 03:54:55 +11:00
riley 19e5843d55 Added testbench for MIPS processor 2026-10-16 03:53:14 +11:00
riley a63d46bc77 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 15:54:38 +11:00
riley 04d1d3e2fe Added control unit. TODO: Test 2026-10-15 15:53:59 +11:00
TroubleElectrical cdde70e6c2 Updated ram.sv to resolve compilation error 2026-10-15 15:42:26 +11:00
TroubleElectrical cd7fecd1c4 Updated code such that it will compile 2026-10-15 15:32:15 +11:00
riley 5fc24f7859 Temp change to make RAM word-aligned 2026-10-15 15:28:27 +11:00
riley 2e042fbd93 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 15:18:09 +11:00
riley a336df9d80 Reworked CPU to use control unit 2026-10-15 15:16:57 +11:00
TroubleElectrical afb6fefe1b Updated Assignment2 with better register file module insantiation 2026-10-15 15:07:41 +11:00
TroubleElectrical 10bf499065 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 14:52:14 +11:00
TroubleElectrical 8c6765eb83 Updated reg file and assignment for compilation 2026-10-15 14:49:32 +11:00
riley 1c93c082ae Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 14:48:06 +11:00
riley d9f44f93df Halfway added imm,branch and mem ops 2026-10-15 14:46:51 +11:00
TroubleElectrical ac1062fbd5 Added Register Display Code 2026-10-15 14:35:10 +11:00
TroubleElectrical 81c05b6531 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 14:27:48 +11:00
TroubleElectrical 6bb6368f6c Added external register inspection code 2026-10-15 14:23:38 +11:00
riley 25ed477df9 Rewrote ternary operator to be less confusing 2026-10-15 14:04:36 +11:00
riley 1e13de9301 Updated assignment2. Created file for testing R-type instructions, still needs to be implemented. Consider using bind to be able to extract inner-scoped variables out for inspection. 2026-10-13 22:26:52 +11:00