New South Wales, Australia
Joined on 2025-02-09
Block a user
fe53955748
Fixed bug in test code where there was a hazzard, despite testing assuming no hazzard. Updated testbench to reflect this (Ln57-62).
74a15cf038
Made ROM binary file configurable via a parameter. Updated assignment2 and assignment3 to reflect this. Added bit slicing in assignment2 for ram/rom addresses.
38fa35fccd
Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module
8f9ec010ac
Updated gate register module to support arbitary delays to prevent littering uper-level code with gatereg->gatereg logic values.
59f7f372f6
Fixed bug where ASU intermediate was being treated as the overflow flag rather than an intermediate.
559ff01d69
Fixed printing annoyance. Added variable dumping to a wavefile. Updated delay to 2 units (as there is 1 unit of clk being high and 1 unit low).
92a0cb17da
Updated assignment 2 to reflect prior changes. Fixed instruction ordering for register file module (again). Fixed typo that limited the space the ALU could write its flags out to. Swapped ordering to be correct when determining if we are storing the result from ALU or MEM.
65be2c2d61
Made sign extension explicit to remove bit indexing (which iverilog doesn't like) and a tad more readable.