riley Riley King-Saunders
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New South Wales, Australia
https://rileyk.au/

Creator of lbs and uniproc

Joined on 2025-02-09
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riley pushed to main at TroubleElectrical/FPGA_Uni 2026-10-15 14:05:05 +11:00
25ed477df9 Rewrote ternary operator to be less confusing
riley pushed to main at TroubleElectrical/FPGA_Uni 2026-10-13 22:27:14 +11:00
1e13de9301 Updated assignment2. Created file for testing R-type instructions, still needs to be implemented. Consider using bind to be able to extract inner-scoped variables out for inspection.
ac6c4cc094 Added module for sign extension. Needs test cases
75ef513efa Added zero flag to ALU and updated testbench to not fail because of it. TODO: Add cases to test the zero flag
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riley pushed to main at TroubleElectrical/FPGA_Uni 2026-10-13 12:45:21 +11:00
f91fe0681a Fixed parameter ordering in instancing
a04d6b92cb Updated register file to use 2^n rather than n
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riley pushed to main at TroubleElectrical/FPGA_Uni 2026-10-13 12:33:29 +11:00
ba9ab863d8 Fixed ordering for instruction counter and added module output gating for writing
riley pushed to main at TroubleElectrical/FPGA_Uni 2026-10-13 12:29:58 +11:00
6d731b5a6b Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni
b9623569cf Partially implemented R-type instructions (still need to write rd values)
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riley pushed to main at TroubleElectrical/FPGA_Uni 2026-10-13 11:56:42 +11:00
979f12b692 Added zero initialization for r0
1faa7fc3f0 Updated ram and rom modules so that naming is more consistent
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riley pushed to main at TroubleElectrical/FPGA_Uni 2026-10-08 15:58:38 +11:00
96ecc8553c Merge branch 'main' of https://git.rileyk.au/TroubleElectrical/FPGA_Uni
dacc49efac TODO
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riley pushed to main at TroubleElectrical/FPGA_Uni 2026-10-08 14:57:00 +11:00
102d5b4b7a Updated RAM interface to be more inline with ROM interface
ab561dd510 Implemented RAM. Possible issue by using async assignments in initial begin.
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riley pushed to main at TroubleElectrical/FPGA_Uni 2026-10-08 14:22:06 +11:00
016fb874e7 Set rom to point to example program
riley pushed to main at TroubleElectrical/FPGA_Uni 2026-10-08 14:18:27 +11:00
76cd7931b6 Realized that, while the assembled is not binary, it is still loadable by verilog.
riley pushed to main at TroubleElectrical/FPGA_Uni 2026-10-08 14:14:26 +11:00
0ef2aeeb48 Added instruction counter and register file
5cb48095ce Merge branch 'main' of https://git.rileyk.au/TroubleElectrical/FPGA_Uni
aab18425f9 Added test assembly code
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riley pushed to assignment-1-submission at TroubleElectrical/FPGA_Uni 2026-09-24 14:19:32 +10:00
riley created branch assignment-1-submission in TroubleElectrical/FPGA_Uni 2026-09-24 14:19:32 +10:00
riley pushed to main at TroubleElectrical/FPGA_Uni 2026-09-16 13:35:55 +10:00
3af4bfc875 Added attribution to submission files
riley pushed to main at TroubleElectrical/FPGA_Uni 2026-09-15 22:00:20 +10:00
900b544bc6 Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken.
riley pushed to main at TroubleElectrical/FPGA_Uni 2026-09-15 21:31:00 +10:00
6a518dcd42 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni
392f1f7a27 Updated shifter testbench to work with 2^n widths rather than bitwidths.
287fc1903d Updated default ASU testbench width to be 4-bit to align with seven segment width for demo
19cd7ac177 Updated ALU and ASU modules to conditionally require seven-segment output logic. Used for the assignment 1 demo and MUST be stripped for assignment 2.
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riley closed issue TroubleElectrical/FPGA_Uni#4 2026-09-14 00:14:06 +10:00
Update ASU to use MUX on B rather than the current logic
riley commented on issue TroubleElectrical/FPGA_Uni#4 2026-09-14 00:14:06 +10:00
Update ASU to use MUX on B rather than the current logic

Done in c4ebde769219a21266c2682c807c01914df54439

riley pushed to main at TroubleElectrical/FPGA_Uni 2026-09-14 00:13:27 +10:00
c4ebde7692 Updated ASU to use an explicit MUX rather than the XOR inversion 'trick' when calculating the operand
riley closed issue TroubleElectrical/FPGA_Uni#3 2026-09-14 00:10:06 +10:00
ALU Testbench needs test cases and ALU needs to be tested.