New South Wales, Australia
Joined on 2025-02-09
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ALU Testbench needs test cases and ALU needs to be tested.
Done in 78efccfe1e389d718e9b8a8c44227d99a0ead578
Update Instruction classifier (and others) to use our own MUX rather than a case statement.
Instruction classifier was re-implemented in 4df723318bf1b41034fe40b330dfee432a08c264 to use explicit combinational logic with a gate depth of 3 and a throughput/pipeline delay of 1. It performs…
ALU Testbench needs test cases and ALU needs to be tested.
Case statements (should) synthesize optimally provided that all possibilities assign to the same variables and that there is a default case. This was implemented in 4df723318bf1b41034fe40b330dfee43…
4df723318b
Ensured case variable assignment is internally consistent with other possibilities to ensure optimal case synthesis
49f539c855
Updated instruction classifier to use combinational logic with a depth of 3 gates (AND, XNOR, HAND)
78efccfe1e
Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output
Update ASU to use MUX on B rather than the current logic
ALU Testbench needs test cases and ALU needs to be tested.
Update Instruction classifier (and others) to use our own MUX rather than a case statement.
cd7074a78c
Need to change instruction classifier implementation to use a more parallel architecture as case statements can produce sequential MUX'es
5acf1c8b87
Fixed bug in adder/subtracter where code assuming width was the bit width was not updated when moving to the 2**N approach required by the assignment. Updated adder/subtracter testbench to correctly instantiate the asser/subtracter and removed unused variable
9794f26137
Fixed error in logic unit testbench where it didn't instansiate the DUT at all as well as some faulty test cases and reset logic
f5a2455849
Added testbench for instruction classifier and fixed compilation errors. Should be fine to synthesise but icarus does not like the constant bit extraction in the always_comb block for some reason.
a89a66d34d
Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage
6668969b03
Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v
0c21734447
Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented