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ALU Testbench needs test cases and ALU needs to be tested. #3

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opened 2026-09-10 16:02:57 +10:00 by riley · 2 comments
riley commented 2026-09-10 16:02:57 +10:00
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We are missing test cases for the ALU.

Might be worth updating the ALU to use our own MUX for gate delay reasons.

We are missing test cases for the ALU. Might be worth updating the ALU to use our own MUX for gate delay reasons.
riley commented 2026-09-13 23:56:53 +10:00
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Case statements (should) synthesize optimally provided that all possibilities assign to the same variables and that there is a default case. This was implemented in 4df723318b.

Case statements (should) synthesize optimally provided that all possibilities assign to the same variables and that there is a default case. This was implemented in 4df723318bf1b41034fe40b330dfee432a08c264.
riley commented 2026-09-14 00:10:06 +10:00
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Done in 78efccfe1e

Done in 78efccfe1e389d718e9b8a8c44227d99a0ead578
riley closed this issue 2026-09-14 00:10:06 +10:00
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Reference: TroubleElectrical/FPGA_Uni#3