TroubleElectrical/FPGA_Uni
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Update ASU to use MUX on B rather than the current logic #4

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opened 2026-09-10 16:05:00 +10:00 by riley · 1 comment
riley commented 2026-09-10 16:05:00 +10:00
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The marking criteria specifically calls out using a 2:1 MUX. Whether A + B^{bitwidth{is_sub[0]}} + is_sub[0] counts as a MUX, who knows.

The marking criteria specifically calls out using a 2:1 MUX. Whether `A + B^{bitwidth{is_sub[0]}} + is_sub[0]` counts as a MUX, who knows.
riley commented 2026-09-14 00:14:06 +10:00
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Done in c4ebde7692

Done in c4ebde769219a21266c2682c807c01914df54439
riley closed this issue 2026-09-14 00:14:06 +10:00
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Reference: TroubleElectrical/FPGA_Uni#4