Update Instruction classifier (and others) to use our own MUX rather than a case statement. #2

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2026-09-10T15:59:52+10:00

riley commented

2026-09-10 15:59:52 +10:00

Using our own MUX would allow us to better spread gates out in parallel, reducing propagation delay.

riley commented

2026-09-14 00:09:20 +10:00

Instruction classifier was re-implemented in 4df723318b to use explicit combinational logic with a gate depth of 3 and a throughput/pipeline delay of 1. It performs an AND, XNOR and HAND (H for horizontal). Note that the actual implementation uses == rather than the XNOR+HAND as to be more succinct and obvious to the synthesizer what we are doing.

out = &( (op & const_mask_1) ~^ const_mask_2);

or equivalently;

out = (op & const_mask_1) == const_mask_2;

This is not the priority decoder that they expected us to implement however I think this actually beats it in gate depth. Maybe not actual gate delay though...

Instruction classifier was re-implemented in 4df723318bf1b41034fe40b330dfee432a08c264 to use explicit combinational logic with a gate depth of 3 and a throughput/pipeline delay of 1. It performs an AND, XNOR and HAND (H for horizontal). Note that the actual implementation uses `==` rather than the XNOR+HAND as to be more succinct and obvious to the synthesizer what we are doing. ```sv out = &( (op & const_mask_1) ~^ const_mask_2); ``` or equivalently; ```sv out = (op & const_mask_1) == const_mask_2; ``` This is not the priority decoder that they expected us to implement however I think this actually beats it in gate depth. Maybe not actual gate delay though...

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Reference: TroubleElectrical/FPGA_Uni#2