TroubleElectrical/FPGA_Uni
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  • c27a04ef73 Implemented instruction classifier on board (Q6) and added blank submission files (for now) TroubleElectrical 2026-09-15 20:00:35 +10:00
  • 9583abd307 Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B) TroubleElectrical 2026-09-15 19:43:28 +10:00
  • 9d0c7011ce Updated ALU (Q4) with 7seg and confirmed operation on board TroubleElectrical 2026-09-15 19:05:04 +10:00
  • 9e5fb6f52b Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board TroubleElectrical 2026-09-15 16:52:48 +10:00
  • 05361dcf70 Added all Testbenches to Modelsim and confirmed working operation TroubleElectrical 2026-09-15 15:15:00 +10:00
  • c4ebde7692 Updated ASU to use an explicit MUX rather than the XOR inversion 'trick' when calculating the operand riley 2026-09-14 00:13:17 +10:00
  • 4df723318b Ensured case variable assignment is internally consistent with other possibilities to ensure optimal case synthesis riley 2026-09-13 23:53:47 +10:00
  • 49f539c855 Updated instruction classifier to use combinational logic with a depth of 3 gates (AND, XNOR, HAND) riley 2026-09-13 23:35:05 +10:00
  • 19ba1bf473 Added header guards to prevent errors from double-inclusions riley 2026-09-13 23:09:08 +10:00
  • 78efccfe1e Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output riley 2026-09-13 23:08:07 +10:00
  • f69f87ccab Just add cases for ALU testbench. The structure of the ALU testbench is now implemented. riley 2026-09-10 15:57:56 +10:00
  • cd7074a78c Need to change instruction classifier implementation to use a more parallel architecture as case statements can produce sequential MUX'es riley 2026-09-10 15:56:59 +10:00
  • 37644c629e Fixed bug of confuddling width with 2^n and w. riley 2026-09-10 15:42:50 +10:00
  • e9feb3cb8d Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni riley 2026-09-10 15:38:50 +10:00
  • 669357ccc0 Implemented ALU. Still needs testbench and testing done. riley 2026-09-10 15:38:36 +10:00
  • a73990b242 Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2) TroubleElectrical 2026-09-10 15:24:44 +10:00
  • dc32347c9b Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3) TroubleElectrical 2026-09-09 14:27:11 +10:00
  • 5acf1c8b87 Fixed bug in adder/subtracter where code assuming width was the bit width was not updated when moving to the 2**N approach required by the assignment. Updated adder/subtracter testbench to correctly instantiate the asser/subtracter and removed unused variable riley 2026-09-08 22:49:22 +10:00
  • 42f4e661dc Implemented shifter and its test bench code fully riley 2026-09-08 22:35:14 +10:00
  • 9794f26137 Fixed error in logic unit testbench where it didn't instansiate the DUT at all as well as some faulty test cases and reset logic riley 2026-09-08 22:00:07 +10:00
  • fabfba7bdd Removed debug statement from instruction classifier testbench riley 2026-09-08 21:44:36 +10:00
  • f5a2455849 Added testbench for instruction classifier and fixed compilation errors. Should be fine to synthesise but icarus does not like the constant bit extraction in the always_comb block for some reason. riley 2026-09-08 21:31:18 +10:00
  • 00d9e3de88 Fixed error where assignment was not within a combinational/sequential block riley 2026-09-08 18:23:27 +10:00
  • 60e5dae43b Added ModelSim folder (and have to add files into it as to allow for different testbench code) TroubleElectrical 2026-09-08 16:32:01 +10:00
  • 2208eb4f16 Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board. TroubleElectrical 2026-09-08 15:36:51 +10:00
  • 32eea036a8 Added projects for A1 q2 to q6 TroubleElectrical 2026-09-04 13:12:33 +10:00
  • 3114cd6b80 Added the updated A1_Q1 Quartus compilation TroubleElectrical 2026-09-03 19:22:52 +10:00
  • b926d71523 Updated seven segment test bench to reflect prior commit riley 2026-09-03 16:58:11 +10:00
  • 3e8aa911ce Made RSIOut the LSB to correspond with wiring configuration riley 2026-09-03 16:56:11 +10:00
  • dd5d044da3 Fixed bit ordering in seven segment truth table and test bench riley 2026-09-03 16:49:46 +10:00
  • 31a4496904 Including quartus prime lite edition project folders for flashing the project to the board TroubleElectrical 2026-09-03 16:34:31 +10:00
  • a89a66d34d Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage riley 2026-09-03 16:32:56 +10:00
  • f881a4126b Inverted seven segment decoder to reflect the common anode riley 2026-09-03 16:27:01 +10:00
  • 6668969b03 Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v riley 2026-09-03 16:05:52 +10:00
  • 0c21734447 Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented riley 2026-09-03 15:25:07 +10:00
  • 41252763d4 Test commit TroubleElectrical 2026-09-03 15:12:25 +10:00
  • 28bfe10398 Initial commit TroubleElectrical 2026-09-03 15:04:27 +10:00