Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

Added Inputs for displaying registers / Program Counter high and low bits,
Assigned pins for Display digits, inputs (Labeled HID) and the clk button

Quartus/A1_Q1/db/seven_seg.db_info

@@ -1,3 +1,3 @@
 Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Version_Index = 604268800
-Creation_Time = Wed Sep 16 09:35:09 2026
+Creation_Time = Tue Oct 13 16:10:56 2026

Quartus/A1_Q1/db/seven_seg.tmw_info

@@ -0,0 +1,4 @@
+start_full_compilation:s
+start_assembler:s-start_full_compilation
+start_timing_analyzer:s-start_full_compilation
+start_eda_netlist_writer:s-start_full_compilation

Quartus/A1_Q6/db/instruction_classifier.db_info

@@ -1,3 +1,3 @@
 Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Version_Index = 604268800
-Creation_Time = Tue Sep 15 19:51:34 2026
+Creation_Time = Thu Sep 24 15:45:52 2026

Quartus/A1_Q6/db/instruction_classifier.tmw_info

@@ -1,7 +1,4 @@
-start_full_compilation:s:00:00:58
+start_full_compilation:s
-start_analysis_synthesis:s:00:00:13-start_full_compilation
+start_assembler:s-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
+start_timing_analyzer:s-start_full_compilation
-start_fitter:s:00:00:29-start_full_compilation
+start_eda_netlist_writer:s-start_full_compilation
-start_assembler:s:00:00:07-start_full_compilation
-start_timing_analyzer:s:00:00:07-start_full_compilation
-start_eda_netlist_writer:s:00:00:02-start_full_compilation

Quartus/A2/assignment2.qpf

@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2025  Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Altera and sold by Altera or its authorized distributors.  Please
+# refer to the Altera Software License Subscription Agreements 
+# on the Quartus Prime software download page.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
+# Date created = 12:03:16  October 13, 2026
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "25.1"
+DATE = "12:03:16  October 13, 2026"
+
+# Revisions
+
+PROJECT_REVISION = "assignment2"

Quartus/A2/assignment2.qsf

@@ -0,0 +1,124 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2025  Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Altera and sold by Altera or its authorized distributors.  Please
+# refer to the Altera Software License Subscription Agreements 
+# on the Quartus Prime software download page.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
+# Date created = 12:03:16  October 13, 2026
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		assignment2_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Intel recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+set_global_assignment -name VERILOG_MACRO QUARTUS_SYNTH
+set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CGXFC5C6F27C7
+set_global_assignment -name TOP_LEVEL_ENTITY assignment2
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:03:16  OCTOBER 13, 2026"
+set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition"
+set_global_assignment -name SYSTEMVERILOG_FILE ../../modules/assignment2.sv
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (SystemVerilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_location_assignment PIN_AE19 -to HID_Register[4]
+set_location_assignment PIN_Y11 -to HID_Register[3]
+set_location_assignment PIN_AC10 -to HID_Register[2]
+set_location_assignment PIN_V10 -to HID_Register[1]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to HID_Register[4]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to HID_Register[3]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to HID_Register[2]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to HID_Register[1]
+set_location_assignment PIN_AB10 -to HID_Register[0]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to HID_Register[0]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to HID_Register
+set_location_assignment PIN_W11 -to HID_PC[0]
+set_location_assignment PIN_AC8 -to HID_Hi_Low[0]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to HID_Hi_Low[0]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to HID_PC[0]
+set_location_assignment PIN_Y16 -to clk[0]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to clk[0]
+set_location_assignment PIN_Y18 -to out_seg_0[7]
+set_location_assignment PIN_Y19 -to out_seg_0[6]
+set_location_assignment PIN_Y20 -to out_seg_0[5]
+set_location_assignment PIN_W18 -to out_seg_0[4]
+set_location_assignment PIN_V17 -to out_seg_0[3]
+set_location_assignment PIN_V18 -to out_seg_0[2]
+set_location_assignment PIN_V19 -to out_seg_0[1]
+set_location_assignment PIN_AF24 -to out_seg_1[7]
+set_location_assignment PIN_AC19 -to out_seg_1[6]
+set_location_assignment PIN_AE25 -to out_seg_1[5]
+set_location_assignment PIN_AE26 -to out_seg_1[4]
+set_location_assignment PIN_AB19 -to out_seg_1[3]
+set_location_assignment PIN_AD26 -to out_seg_1[2]
+set_location_assignment PIN_AA18 -to out_seg_1[1]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_0[7]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_0[6]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_0[5]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_0[4]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_0[3]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_0[2]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_0[1]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[7]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[6]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[5]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[4]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[3]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[2]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[1]
+set_location_assignment PIN_AD7 -to out_seg_2[1]
+set_location_assignment PIN_W20 -to out_seg_2[7]
+set_location_assignment PIN_AD6 -to out_seg_2[2]
+set_location_assignment PIN_U20 -to out_seg_2[3]
+set_location_assignment PIN_V22 -to out_seg_2[4]
+set_location_assignment PIN_V20 -to out_seg_2[5]
+set_location_assignment PIN_W21 -to out_seg_2[6]
+set_location_assignment PIN_AC22 -to out_seg_3[7]
+set_location_assignment PIN_Y24 -to out_seg_3[1]
+set_location_assignment PIN_Y23 -to out_seg_3[2]
+set_location_assignment PIN_AA23 -to out_seg_3[3]
+set_location_assignment PIN_AA22 -to out_seg_3[4]
+set_location_assignment PIN_AC24 -to out_seg_3[5]
+set_location_assignment PIN_AC23 -to out_seg_3[6]
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Quartus/A2/c5_pin_model_dump.txt

@@ -0,0 +1,88 @@
+io_4iomodule_c5_index: 61gpio_index: 2
+io_4iomodule_c5_index: 62gpio_index: 348
+io_4iomodule_c5_index: 40gpio_index: 6
+io_4iomodule_c5_index: 59gpio_index: 344
+io_4iomodule_c5_index: 31gpio_index: 10
+io_4iomodule_c5_index: 35gpio_index: 340
+io_4iomodule_c5_index: 42gpio_index: 14
+io_4iomodule_c5_index: 19gpio_index: 336
+io_4iomodule_c5_index: 29gpio_index: 19
+io_4iomodule_c5_index: 9gpio_index: 332
+io_4iomodule_c5_index: 34gpio_index: 22
+io_4iomodule_c5_index: 25gpio_index: 328
+io_4iomodule_c5_index: 17gpio_index: 27
+io_4iomodule_c5_index: 44gpio_index: 324
+io_4iomodule_c5_index: 57gpio_index: 30
+io_4iomodule_c5_index: 13gpio_index: 320
+io_4iomodule_c5_index: 5gpio_index: 35
+io_4iomodule_c5_index: 39gpio_index: 316
+io_4iomodule_c5_index: 14gpio_index: 38
+io_4iomodule_c5_index: 27gpio_index: 312
+io_4iomodule_c5_index: 21gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 308
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 26gpio_index: 304
+io_4iomodule_c5_index: 1gpio_index: 51
+io_4iomodule_c5_index: 38gpio_index: 300
+io_4iomodule_c5_index: 50gpio_index: 54
+io_4iomodule_c5_index: 36gpio_index: 296
+io_4iomodule_c5_index: 11gpio_index: 59
+io_4iomodule_c5_index: 2gpio_index: 292
+io_4iomodule_c5_index: 4gpio_index: 62
+io_4iomodule_c5_index: 6gpio_index: 288
+io_4iomodule_c5_index: 48gpio_index: 67
+io_4iomodule_c5_index: 24gpio_index: 284
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 12gpio_index: 280
+io_4iomodule_c5_index: 49gpio_index: 75
+io_4iomodule_c5_index: 63gpio_index: 276
+io_4iomodule_c5_index: 41gpio_index: 78
+io_4iomodule_c5_index: 37gpio_index: 272
+io_4iomodule_c5_index: 3gpio_index: 83
+io_4iomodule_c5_index: 33gpio_index: 268
+io_4iomodule_c5_index: 22gpio_index: 86
+io_4iomodule_c5_index: 54gpio_index: 264
+io_4iomodule_c5_index: 56gpio_index: 91
+io_4iomodule_c5_index: 32gpio_index: 260
+io_4iomodule_c5_index: 53gpio_index: 94
+io_4iomodule_c5_index: 52gpio_index: 256
+io_4iomodule_c5_index: 28gpio_index: 99
+io_4iomodule_c5_index: 45gpio_index: 252
+io_4iomodule_c5_index: 10gpio_index: 102
+io_4iomodule_c5_index: 43gpio_index: 248
+io_4iomodule_c5_index: 15gpio_index: 107
+io_4iomodule_c5_index: 7gpio_index: 244
+io_4iomodule_c5_index: 55gpio_index: 110
+io_4iomodule_c5_index: 60gpio_index: 240
+io_4iomodule_c5_index: 18gpio_index: 115
+io_4iomodule_c5_index: 58gpio_index: 236
+io_4iomodule_c5_index: 46gpio_index: 118
+io_4iomodule_c5_index: 30gpio_index: 232
+io_4iomodule_c5_index: 16gpio_index: 123
+io_4iomodule_c5_index: 47gpio_index: 228
+io_4iomodule_c5_index: 51gpio_index: 126
+io_4iomodule_c5_index: 23gpio_index: 224
+io_4iomodule_h_c5_index: 0gpio_index: 129
+io_4iomodule_h_c5_index: 18gpio_index: 133
+io_4iomodule_h_c5_index: 15gpio_index: 137
+io_4iomodule_h_c5_index: 16gpio_index: 141
+io_4iomodule_h_c5_index: 20gpio_index: 144
+io_4iomodule_h_c5_index: 23gpio_index: 148
+io_4iomodule_h_c5_index: 12gpio_index: 152
+io_4iomodule_h_c5_index: 9gpio_index: 156
+io_4iomodule_h_c5_index: 1gpio_index: 160
+io_4iomodule_h_c5_index: 5gpio_index: 164
+io_4iomodule_h_c5_index: 21gpio_index: 168
+io_4iomodule_h_c5_index: 6gpio_index: 172
+io_4iomodule_h_c5_index: 17gpio_index: 176
+io_4iomodule_h_c5_index: 2gpio_index: 180
+io_4iomodule_h_c5_index: 4gpio_index: 184
+io_4iomodule_h_c5_index: 3gpio_index: 188
+io_4iomodule_h_c5_index: 14gpio_index: 192
+io_4iomodule_h_c5_index: 7gpio_index: 196
+io_4iomodule_h_c5_index: 19gpio_index: 200
+io_4iomodule_h_c5_index: 11gpio_index: 204
+io_4iomodule_h_c5_index: 8gpio_index: 208
+io_4iomodule_h_c5_index: 13gpio_index: 212
+io_4iomodule_h_c5_index: 22gpio_index: 216
+io_4iomodule_h_c5_index: 10gpio_index: 220