TroubleElectrical d2ba06b255 Added Hazard Unit file (tested compiling correctly) labelled variables inside off of the Assignment 3 Questions PDF Figure 2. ...

Also have a placeholder MUX to place before the ALU for adding hazard unit functionality

2026-11-08 12:32:40 +11:00

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alu.sv

Fixed bug where ASU intermediate was being treated as the overflow flag rather than an intermediate.

2026-10-16 12:33:04 +11:00

alu.sv.bak

Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)

2026-09-09 14:27:11 +10:00

assignment2.sv

Made ROM binary file configurable via a parameter. Updated assignment2 and assignment3 to reflect this. Added bit slicing in assignment2 for ram/rom addresses.

2026-11-05 14:27:01 +11:00

assignment2.sv.bak

Updated assignment 2 dependency modules (currently 8 errors in compile)

2026-10-13 12:23:52 +11:00

assignment3.sv

Added Hazard Unit file (tested compiling correctly) labelled variables inside off of the Assignment 3 Questions PDF Figure 2.

2026-11-08 12:32:40 +11:00

asu.sv

Removed seven segment code from alu and asu

2026-09-24 15:37:48 +10:00

asu.sv.bak

Added ModelSim folder (and have to add files into it as to allow for different testbench code)

2026-09-08 16:32:01 +10:00

ByteIM.sv

Fixed ByteIM.sv and removed seven seg from A3 code

2026-11-05 14:33:41 +11:00

control_unit.sv

Updated assignment 2 to reflect prior changes. Fixed instruction ordering for register file module (again). Fixed typo that limited the space the ALU could write its flags out to. Swapped ordering to be correct when determining if we are storing the result from ALU or MEM.

2026-10-16 11:38:35 +11:00

gatereg.sv

Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module

2026-11-05 14:10:13 +11:00

hazard_unit.sv

Added Hazard Unit file (tested compiling correctly) labelled variables inside off of the Assignment 3 Questions PDF Figure 2.

2026-11-08 12:32:40 +11:00

instruction_classifier.sv

Updated instruction classifier to use combinational logic with a depth of 3 gates (AND, XNOR, HAND)

2026-09-13 23:35:05 +10:00

instruction_counter.sv

Added explicit rst input to RAM and PC as well as the MIPS processor.

2026-10-16 12:11:19 +11:00

lu.sv

Added comments to Logic Unit (Q2) and added to submission file

2026-09-16 12:38:06 +10:00

lu.sv.bak

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00

ram.sv

Fixed bug where ram datawidth was not 2^N.

2026-10-20 16:01:34 +11:00

register_file.sv

Added initialisation blocks for PC and GPR's

2026-10-16 11:33:45 +11:00

rom.sv

Made ROM binary file configurable via a parameter. Updated assignment2 and assignment3 to reflect this. Added bit slicing in assignment2 for ram/rom addresses.

2026-11-05 14:27:01 +11:00

seven_seg_4digit.sv

Added code to display current PC,

2026-10-16 14:27:29 +11:00

seven_seg.sv

Added header guards to prevent errors from double-inclusions

2026-09-13 23:09:08 +10:00

shifter.sv

Added Q5 comments and sumbission

2026-09-16 12:54:18 +10:00

shifter.sv.bak

Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)

2026-09-15 19:43:28 +10:00

sign_extender.sv

Repaired Sign extender module again to ensure only combinational logic used

2026-10-22 15:53:15 +11:00