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FPGA_Uni/modules/assignment2.sv.bak

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`include "rom.sv"
`include "ram.sv"
`include "instruction_counter.sv"
`include "instruction_classifier.sv"
`include "alu.sv"
module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
logic [romsz-1:0] pc_addr;
logic [0:0] pc_we;
logic [2**width-1:0] instruction;
instruction_counter pc #(romsz)(clk, pc_we, pc_addr, pc_addr);
ROM rom #(romsz, 2**width)();
RAM ram #(ramsz, 2**width)();
alu alu #(width)();
endmodule