riley
92a0cb17da
Added a QUARTUS_SYNTH around the display logic at the end of the module. Partially fixed control_unit module, still seems to need some changes as branching doesn't appear to work at all.
37 lines
1.5 KiB
Systemverilog
37 lines
1.5 KiB
Systemverilog
`ifndef CONTROL_UNIT_H
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`define CONTROL_UNIT_H
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`include "instruction_classifier.sv"
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module control_unit (
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input logic [5:0] op, input logic [5:0] func,
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output logic [0:0] M2R, // Enables writing data stored in memory at the address (rs/A)+(ALU_SRC ? imm : rt/B) into rd
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output logic [0:0] M2W, // Enable writing data stored in rt/B into memory at the address (rs/A)+(ALU_SRC ? imm : rt/B)
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output logic [0:0] B, // AND'ed with flags to determine if branch is permitted
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output logic [3:0] ALU_FN, // Controls what function the ALU is to perform
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output logic [0:0] ALU_SRC, // Controls whether to use the rt/B register read port or 16-bit immediate
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output logic [0:0] RDST, // Controls where to look in the instruction encoding for the register write address
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output logic [0:0] RW // Enable register write port
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);
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logic [0:0] TYPE_R;
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logic [0:0] TYPE_B1;
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logic [0:0] TYPE_J;
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logic [0:0] TYPE_B2;
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logic [0:0] TYPE_I;
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logic [0:0] TYPE_F;
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logic [0:0] TYPE_M;
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instruction_classifier CLASSIFIER (op, TYPE_R, TYPE_B1, TYPE_J, TYPE_B2, TYPE_I, TYPE_F, TYPE_M);
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always_comb begin
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M2R = TYPE_M & ~((op & 6'b001000) >> 3);
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M2W = TYPE_M & ((op & 6'b001000) >> 3);
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B = TYPE_B1 | TYPE_B2 | TYPE_J;
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ALU_FN = (func & {(4){TYPE_R}}) | ( {2'b00, (op & 6'b000011)} & {(4){TYPE_I}}) | (4'b0010 & {4{TYPE_B1 | TYPE_B2}});
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ALU_SRC = TYPE_I | TYPE_M;
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RDST = TYPE_R; // Imm ops store back into rt
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RW = TYPE_R | TYPE_I | M2R;
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end
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endmodule
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`endif
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