Merge branch 'main' of https://git.rileyk.au/TroubleElectrical/FPGA_Uni

Quartus/A1_Q1/db/seven_seg.tmw_info

@@ -0,0 +1,4 @@
+start_full_compilation:s
+start_assembler:s-start_full_compilation
+start_timing_analyzer:s-start_full_compilation
+start_eda_netlist_writer:s-start_full_compilation

Quartus/A1_Q6/db/instruction_classifier.db_info

@@ -1,3 +1,3 @@
 Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Version_Index = 604268800
-Creation_Time = Tue Sep 15 19:51:34 2026
+Creation_Time = Thu Sep 24 15:45:52 2026

Quartus/A1_Q6/db/instruction_classifier.tmw_info

@@ -1,7 +1,4 @@
-start_full_compilation:s:00:00:58
-start_analysis_synthesis:s:00:00:13-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:29-start_full_compilation
-start_assembler:s:00:00:07-start_full_compilation
-start_timing_analyzer:s:00:00:07-start_full_compilation
-start_eda_netlist_writer:s:00:00:02-start_full_compilation
+start_full_compilation:s
+start_assembler:s-start_full_compilation
+start_timing_analyzer:s-start_full_compilation
+start_eda_netlist_writer:s-start_full_compilation

asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt

@@ -0,0 +1,51 @@
+//      $File: NewcastleUniversity/ELEC4720/2026s2/src/Code/Assignment/Ass-02-Demo.txt $
+//      $Date: 2026-10-07 01:48:03 +1100 (Wed, 07 Oct 2026) $
+//  $Revision: 2523 $
+//    $Author: Peter $
+//
+//     Course: ELEC4720(2026s2) Programmable Logic Design
+//     School: Engineering
+// University: The University of Newcastle
+//    Address: CALLAGHAN NSW 2308 Australia
+//
+//     Author: Dr Peter Stepien
+//      Email: peter.stepien@newcastle.edu.au
+//  Copyright: 2026
+	
+// Assignment 2 Demonstration Program (all instructions)
+
+// main:
+// Initialise some registers
+01084023 // subu $t0, $t0, $t0
+25090007 // addiu $t1, $t0, 7
+
+// Memory operations
+ad090000 // sw $t1, 0x0000($t0)
+8d0a0000 // lw $t2, 0x0000($t0)
+
+// Remaining arithmetic
+012a5821 // addu $t3, $t1, $t2
+012b6022 // sub $t4, $t1, $t3
+212d0003 // addi $t5, $t1, 3
+018d7020 // add $t6, $t4, $t5 
+
+// Logical
+012d8024 // and $s0, $t1, $t5
+012d8825 // or $s1, $t1, $t5 
+012d9026 // xor $s2, $t1, $t5
+012d9827 // nor $s3, $t1, $t5
+
+// Comparison
+018ea02a // slt $s4, $t4, $t6 
+018ea82b // sltu $s5, $t4, $t6
+
+// Loop to test branch
+// loop:
+25080001 // addiu $t0, $t0, 1 
+010db02b // sltu $s6, $t0, $t5
+12d4fffd // beq $s6, $s4, loop
+
+// Endless loop at end of program (FPGA)
+// finish:
+12d6ffff // beq $s6, $s6, finish
+

asm/src/ELEC4720-2026s2-Ass-02-Demo.s

@@ -0,0 +1,61 @@
+#      $File: NewcastleUniversity/ELEC4720/2026s2/src/Code/Assignment/Ass-02-Demo.s $
+#      $Date: 2026-10-07 01:54:03 +1100 (Wed, 07 Oct 2026) $
+#  $Revision: 2525 $
+#    $Author: Peter $
+#
+#     Course: ELEC4720(2026s2) Programmable Logic Design
+#     School: Engineering
+# University: The University of Newcastle
+#    Address: CALLAGHAN NSW 2308 Australia
+#
+#     Author: Dr Peter Stepien
+#      Email: peter.stepien@newcastle.edu.au
+#  Copyright: 2026
+	
+# Assignment 2 Demonstration Program (all instructions)
+
+	.text
+	.globl main
+	.globl loop
+	.globl finish
+
+main:
+	# Initialise some registers
+	subu $t0, $t0, $t0 # Set t0 = 0 (R8, modified below)
+	addiu $t1, $t0, 7  # Set t1 = 7 (R9)
+
+	# Memory operations
+	sw $t1, 0x10000000($t0) # Save t1 to memory (change to 0x0000 for FPGA)
+	lw $t2, 0x10000000($t0) # Load t2 from memory (change to 0x0000 for FPGA) (R10)
+	
+	# Remaining arithmetic
+	addu $t3, $t1, $t2 # Unsigned t3 = t1 + t2 = 14 (R11)
+	sub $t4, $t1, $t3  # Signed   t4 = t1 - t3 = -7 (R12)
+	addi $t5, $t1, 3   # Signed   t5 = t1 +  3 = 10 (R13)
+	add $t6, $t4, $t5  # Signed   t6 = t4 + t5 =  3 (R14)
+
+	# Logical (t1 = 0000..0111, t5 = 0000..1010)
+	and $s0, $t1, $t5  # s0 = t1 and t5 =   2 (0000..0010) (R16)
+	or $s1, $t1, $t5   # s1 = t1 or  t5 =  15 (0000..1111) (R17)
+	xor $s2, $t1, $t5  # s2 = t1 xor t5 =  13 (0000..1101) (R18)
+	nor $s3, $t1, $t5  # s3 = t1 nor t5 = -16 (1111..0000) (R19)
+
+	# Comparison
+	slt $s4, $t4, $t6  # Signed   s4 = t4 < t6 = 1 (true)  (R20)
+	sltu $s5, $t4, $t6 # Unsigned s5 = t4 < t6 = 0 (false) (R21)
+
+	# Loop to test branch
+loop:
+	addiu $t0, $t0, 1  # Increment counter
+	sltu $s6, $t0, $t5 # Unsigned s6 = t0 < t5 (Last 0) (R22)
+	beq $s6, $s4, loop # Loop if s6 == s4
+
+    # Endless loop at end of program (FPGA)
+finish:
+    # beq $s6, $s6, finish # Endless loop
+    
+    # Alternative system call to exit program (spim)
+	li $v0, 10
+	syscall
+
+# END OF FILE

modules/ByteIM.sv

@@ -0,0 +1,14 @@
+`include "rom.sv"
+
+module ByteIM #(parameter m=5,n=2) (
+    input logic [m-1:0] Ad,
+    output logic [(2**n)*8-1:0] Dout );
+
+    // 2**n byte wide words
+    // m bit wide byte address
+    // 2**m bytes of memory
+    // 2**(m-n) memory words
+    // 2**(n+3) bit wide words
+    // Reads the whole word that contains the addressed byte
+    ROM #(m-n,2**(n+3)) wordrom(Ad[m-1:n],Dout)
+endmodule

modules/alu.sv

@@ -3,31 +3,19 @@
 
 `include "asu.sv"
 `include "lu.sv"
-`include "seven_seg.sv"
 
 // flags[0:0] = Cout
 // flags[1:1] = Overflow
 module alu #(parameter width=2)(input logic [3:0] op,
     input logic [2**width-1:0] A, input logic [2**width-1:0] B,
     output logic [2**width-1:0] OUT_1, output logic[1:0] flags
-`ifdef SYNTHESIS
-	, output logic [7:0] out_seg1);
-`else
     );
-`endif
     // intermediate logic for handling asu output
     logic [0:0] asu_op;
     logic [2**width-1:0] asu_out;
     logic [1:0] asu_flags;
-    logic [7:0] asu_seven_seg_out;
 
-    // NOTE: For demo only
-    // TODO: Strip this for assignment 2
-    `ifdef SYNTHESIS
-        asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1], asu_seven_seg_out);
-    `else
     asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
-    `endif
 
     logic [2**width-1:0] lu_out;
     lu #(width) logic_unit(op[1:0], A, B, lu_out);
@@ -47,11 +35,5 @@ module alu #(parameter width=2)(input logic [3:0] op,
             default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
         endcase
     end
-
-    // NOTE: For demo only
-    // TODO: Strip this for assignment 2
-    `ifdef SYNTHESIS
-	    seven_seg dut(OUT_1, 1'b1, out_seg1);
-    `endif
 endmodule
 `endif

modules/assignment2.sv

@@ -0,0 +1,19 @@
+`include "rom.sv"
+`include "ram.sv"
+`include "instruction_counter.sv"
+`include "instruction_classifier.sv"
+`include "alu.sv"
+
+
+module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
+    
+    logic [romsz-1:0] pc_addr;
+    logic [0:0] pc_we;
+    logic [2**width-1:0] instruction;
+
+    instruction_counter pc #(romsz)(clk, pc_we, pc_addr, pc_addr);
+    ROM rom #(romsz, 2**width)();
+    RAM ram #(ramsz,  2**width)();
+    alu alu #(width)();
+
+endmodule

modules/asu.sv

@@ -1,20 +1,14 @@
 `ifndef ASU_H_SV
 `define ASU_H_SV
 
-`include "seven_seg.sv"
 module asu #(parameter width = 2)(
 	input logic [0:0] op,
 	input logic[2**width-1:0] A, input logic[2**width-1:0] B,
     output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN
-// Used to switch between demo mode and testbench mode
-// TODO: Strip for assignment 2
-`ifdef SYNTHESIS
-	, output logic[7:0] out_seg_1);
-`else
     );
-`endif
 
     logic [2**width-1:0] operand;
+
     always_comb begin
         // A + (sub) ? B : -B
         // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
@@ -27,10 +21,5 @@ module asu #(parameter width = 2)(
     // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
     assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
 
-	// Include seven segment visual output for hardware builds only
-    // TODO: Strip this for assignment 2 outright
-    `ifdef SYNTHESIS 
-	    seven_seg dut(OUT_1, 1'b1, out_seg_1);
-    `endif
 endmodule
 `endif

modules/instruction_counter.sv

@@ -0,0 +1,21 @@
+`ifndef INSTRUCTION_COUNTER_H
+`define INSTRUCTION_COUNTER_H
+
+module instruction_counter #(parameter width=5)(
+    input logic [0:0] clk, input logic [0:0] we,
+    input logic [2**width-1:0] W,
+    output logic [2**width-1:0] addr
+);
+
+    logic [2**width-1:0] pc;
+    always_ff (@posedge clk) begin
+        if (we) begin
+            pc <= W
+        else
+            pc <= pc + 4;
+        end
+    end
+
+    assign addr = pc;
+endmodule
+`endif

modules/ram.sv

@@ -0,0 +1,25 @@
+module RAM #(addrwidth=9, datawidth=5)(
+    input logic [0:0] clk,
+    input logic [2**addrwidth-1:0] addr,
+    input logic [0:0] we,
+    input logic [datawidth-1:0] data_in,
+    output logic [datawidth-1:0] data_out
+);
+
+    logic [7:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0];
+
+    // NOTE: Possible issue with assignments still pending by end of initial block
+    initial begin
+        for (integer ADDR = 0; ADDR < 2**(addrwidth+$clog2(datawidth)-3); ++ADDR) begin
+            mem[ADDR] <= 8'b0;
+        end
+    end
+
+    always_ff(@posedge clk) begin
+        if (we) begin
+            mem[addr] <= data_in;
+        end
+    end
+    assign data_out = mem[addr];
+
+endmodule;

modules/register_file.sv

@@ -0,0 +1,22 @@
+`ifndef REGISTER_FILE_H
+`define REGISTER_FILE_H
+
+module register_file #(parameter width=5, parameter nregs=32)(
+    input logic [0:0] clk, input logic[0:0] we,
+    input logic [$clog(nregs)-1:0] WA, input logic [2**width-1:0] WD,
+    input logic [$clog(nregs)-1:0] RA1, output logic [2**width-1:0] RD1,
+    input logic [$clog(nregs)-1:0] RA2, output logic [2**width-1:0] RD2
+);
+    localparam BW = 2**width;
+    logic [2**width-1:0] regs[nregs];
+
+    always_ff @(posedge clk) begin
+        if (we & (WA != {(2**width){1'b0}} )) begin
+            regs[WA] <= WD;
+        end
+    end
+
+    assign RD1 = regs[RA1];
+    assign RD2 = regs[RA2];
+endmodule
+`endif

modules/rom.sv

@@ -0,0 +1,19 @@
+
+module ROM #(parameter m=7,p=4) (
+        input logic [m-1:0] Ad,
+        output logic [p-1:0] Dout
+    );
+    
+    logic [p-1:0] mem[2**m-1:0];
+    assign Dout = mem[Ad];
+
+    //Load the program in memory
+    // The machine code stored in text file program.dat written in Hex format
+    initial begin
+        `ifdef QUARTUS_BUILD
+            $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
+        `else
+            $readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
+        `endif
+    end
+endmodule // end ROM module