23 lines
656 B
Systemverilog
23 lines
656 B
Systemverilog
`ifndef REGISTER_FILE_H
|
|
`define REGISTER_FILE_H
|
|
|
|
module register_file #(parameter width=5, parameter nregs=32)(
|
|
input logic [0:0] clk, input logic[0:0] we,
|
|
input logic [$clog(nregs)-1:0] WA, input logic [2**width-1:0] WD,
|
|
input logic [$clog(nregs)-1:0] RA1, output logic [2**width-1:0] RD1,
|
|
input logic [$clog(nregs)-1:0] RA2, output logic [2**width-1:0] RD2
|
|
);
|
|
localparam BW = 2**width;
|
|
logic [2**width-1:0] regs[nregs];
|
|
|
|
always_ff @(posedge clk) begin
|
|
if (we & (WA != {(2**width){1'b0}} )) begin
|
|
regs[WA] <= WD;
|
|
end
|
|
end
|
|
|
|
assign RD1 = regs[RA1];
|
|
assign RD2 = regs[RA2];
|
|
endmodule
|
|
`endif
|