62 lines
1.9 KiB
ArmAsm
62 lines
1.9 KiB
ArmAsm
# $File: NewcastleUniversity/ELEC4720/2026s2/src/Code/Assignment/Ass-02-Demo.s $
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# $Date: 2026-10-07 01:54:03 +1100 (Wed, 07 Oct 2026) $
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# $Revision: 2525 $
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# $Author: Peter $
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#
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# Course: ELEC4720(2026s2) Programmable Logic Design
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# School: Engineering
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# University: The University of Newcastle
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# Address: CALLAGHAN NSW 2308 Australia
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#
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# Author: Dr Peter Stepien
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# Email: peter.stepien@newcastle.edu.au
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# Copyright: 2026
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# Assignment 2 Demonstration Program (all instructions)
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.text
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.globl main
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.globl loop
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.globl finish
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main:
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# Initialise some registers
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subu $t0, $t0, $t0 # Set t0 = 0 (R8, modified below)
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addiu $t1, $t0, 7 # Set t1 = 7 (R9)
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# Memory operations
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sw $t1, 0x10000000($t0) # Save t1 to memory (change to 0x0000 for FPGA)
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lw $t2, 0x10000000($t0) # Load t2 from memory (change to 0x0000 for FPGA) (R10)
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# Remaining arithmetic
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addu $t3, $t1, $t2 # Unsigned t3 = t1 + t2 = 14 (R11)
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sub $t4, $t1, $t3 # Signed t4 = t1 - t3 = -7 (R12)
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addi $t5, $t1, 3 # Signed t5 = t1 + 3 = 10 (R13)
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add $t6, $t4, $t5 # Signed t6 = t4 + t5 = 3 (R14)
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# Logical (t1 = 0000..0111, t5 = 0000..1010)
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and $s0, $t1, $t5 # s0 = t1 and t5 = 2 (0000..0010) (R16)
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or $s1, $t1, $t5 # s1 = t1 or t5 = 15 (0000..1111) (R17)
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xor $s2, $t1, $t5 # s2 = t1 xor t5 = 13 (0000..1101) (R18)
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nor $s3, $t1, $t5 # s3 = t1 nor t5 = -16 (1111..0000) (R19)
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# Comparison
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slt $s4, $t4, $t6 # Signed s4 = t4 < t6 = 1 (true) (R20)
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sltu $s5, $t4, $t6 # Unsigned s5 = t4 < t6 = 0 (false) (R21)
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# Loop to test branch
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loop:
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addiu $t0, $t0, 1 # Increment counter
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sltu $s6, $t0, $t5 # Unsigned s6 = t0 < t5 (Last 0) (R22)
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beq $s6, $s4, loop # Loop if s6 == s4
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# Endless loop at end of program (FPGA)
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finish:
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# beq $s6, $s6, finish # Endless loop
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# Alternative system call to exit program (spim)
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li $v0, 10
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syscall
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# END OF FILE
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