Added attribution to submission files

Renamed submission folder to fix typo.

ModelSim/asu_tb.sv

@@ -1,6 +1,6 @@
 `include "asu.sv"
 
-module asu_tb #(width=8)();
+module asu_tb #(width=4)();
     logic [0:0] op;
     logic [width-1:0] A;
     logic [width-1:0] B;

ModelSim/shifter.sv

@@ -1,8 +1,8 @@
 `ifndef SHIFTER_H_SV
 `define SHIFTER_H_SV
-module shifter #(width=8)(input logic [2:0] op,
-    input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B,
-    output logic[width-1:0] OUT_1);
+module shifter #(width=2)(input logic [2:0] op,
+    input logic[2**width-1:0] A, input logic[2**width-1:0] B, input logic[width-1:0] C,
+    output logic[2**width-1:0] OUT_1);
 
     always_comb begin
         case (op)

ModelSim/shifter_tb.sv

@@ -1,62 +1,62 @@
 `include "shifter.sv"
-module shifter_tb #(width=8)();
+module shifter_tb #(width=4)();
     logic [2:0] op;
-    logic [width-1:0] Y;
-    logic [width-1:0] A_in;
-    logic [$clog2(width)-1:0] B_in;
+    logic [2**width-1:0] Y;
+    logic [2**width-1:0] A_in;
+    logic [2**width-1:0] B_in;
     logic [width-1:0] C_in;
 
     logic [2:0] ops[6];
-    logic [width-1:0] A[6];
-    logic [$clog2(width)-1:0] B[6];
+    logic [2**width-1:0] A[6];
+    logic [2**width-1:0] B[6];
     logic [width-1:0] C[6];
-    logic [width-1:0] Y_exp[6];
+    logic [2**width-1:0] Y_exp[6];
 
-    shifter #(width) dut(op, A_in,C_in,B_in,Y);
+    shifter #(width) dut(op, A_in,B_in,C_in,Y);
 
     integer error_count;
     initial begin
         // Test left shift by C
         ops[0] = 3'b000;
-        A[0] = {{(width-1){1'b0}}, {1'b1}};
+        A[0] = {{(2**width-1){1'b0}}, {1'b1}};
         C[0] = {{(width-1){1'b0}}, {1'b1}};
-        B[0] = {width{1'b0}};
-        Y_exp[0] = {{(width-2){1'b0}}, {2'b10}};
+        B[0] = {2**width{1'b0}};
+        Y_exp[0] = {{(2**width-2){1'b0}}, {2'b10}};
 
         // Test left shift by B
         ops[1] = 3'b100;
-        A[1] = {{(width-1){1'b0}}, {1'b1}};
+        A[1] = {{(2**width-1){1'b0}}, {1'b1}};
         C[1] = {{(width-1){1'b0}}, {1'b1}};
-        B[1] = {{($clog2(width)-2){1'b0}}, 2'b10};
-        Y_exp[1] = {{(width-3){1'b0}}, {3'b100}};
+        B[1] = {{(2**width-2){1'b0}}, 2'b10};
+        Y_exp[1] = {{(2**width-3){1'b0}}, {3'b100}};
 
         // Test Logical right shift by C
         ops[2] = 3'b001;
-        A[2] = {{(width-2){1'b0}}, {2'b10}};
+        A[2] = {{(2**width-2){1'b0}}, {2'b10}};
         C[2] = {{(width-1){1'b0}}, {1'b1}};
-        B[2] = {width{1'b0}};
-        Y_exp[2] = {{(width-1){1'b0}}, {1'b1}};
+        B[2] = {2**width{1'b0}};
+        Y_exp[2] = {{(2**width-1){1'b0}}, {1'b1}};
 
         // Test Logical right shift by B
         ops[3] = 3'b101;
-        A[3] = {{(width-1){1'b0}}, {2'b10}};
+        A[3] = {{(2**width-1){1'b0}}, {2'b10}};
         C[3] = {{(width-1){1'b0}}, {1'b1}};
-        B[3] = {{($clog2(width)-2){1'b0}}, 2'b10};
-        Y_exp[3] = {{(width-1){1'b0}}, {1'b0}};
+        B[3] = {{(2**width-2){1'b0}}, 2'b10};
+        Y_exp[3] = {{(2**width-1){1'b0}}, {1'b0}};
 
         // Test arithmetic shift right by C
         ops[4] = 3'b011;
-        A[4] = {{(width-1){1'b1}}, 1'b0};   // -2
+        A[4] = {{(2**width-1){1'b1}}, 1'b0};   // -2
         C[4] = {{(width-1){1'b0}}, 1'b1};   // 1
-        B[4] = {{(width-2){1'b0}}, 2'b10};  // 2
-        Y_exp[4] = {width{1'b1}};           // -1
+        B[4] = {{(2**width-2){1'b0}}, 2'b10};  // 2
+        Y_exp[4] = {2**width{1'b1}};           // -1
 
         // Test arithmetic shift right by B
         ops[5] = 3'b111;
-        A[5] = {{(width-2){1'b1}}, 2'b00};   // -4
+        A[5] = {{(2**width-2){1'b1}}, 2'b00};   // -4
         C[5] = {{(width-1){1'b0}}, 1'b1};   // 1
-        B[5] = {{(width-2){1'b0}}, 2'b10};  // 2
-        Y_exp[5] = {width{1'b1}};           // -1
+        B[5] = {{(2**width-2){1'b0}}, 2'b10};  // 2
+        Y_exp[5] = {2**width{1'b1}};           // -1
 
         error_count = 0;
         $display("Beginning Shifter tests");

Quartus/A1_Q1/db/seven_seg.db_info

@@ -1,3 +1,3 @@
 Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Version_Index = 604268800
-Creation_Time = Tue Sep 15 20:07:32 2026
+Creation_Time = Wed Sep 16 09:35:09 2026

Quartus/A1_Q1/db/seven_seg.tmw_info

@@ -1,7 +0,0 @@
-start_full_compilation:s:00:00:59
-start_analysis_synthesis:s:00:00:12-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:31-start_full_compilation
-start_assembler:s:00:00:07-start_full_compilation
-start_timing_analyzer:s:00:00:07-start_full_compilation
-start_eda_netlist_writer:s:00:00:02-start_full_compilation

Quartus/A1_Q1/seven_seg.sv

@@ -2,12 +2,12 @@
 `define SEVEN_SEG_H_SV
 
 module seven_seg(
-input logic [3:0] num, 
-input logic [0:0] rbi_inv, 
-output logic [7:0] segments);
+input logic [3:0] num,          // Input binary
+input logic [0:0] rbi_inv,      // Ripple blanking input
+output logic [7:0] segments);   // segent[0] = Ripple blanking out, segment[1] to segment[7] 7 seg LEDs
 
 	always_comb begin 
-		case (num)
+		case (num) // implement truth table as case statement
 			4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000); // zero or blank
 			4'b0001: segments = ~(8'b00001101);
 			4'b0010: segments = ~(8'b10110111);
@@ -35,8 +35,6 @@ input logic [3:0] a,			// right
 output logic [7:0] seg_b,	// left
 output logic [7:0] seg_a); // right
 	
-	logic rbo_b;
-	
 	// seg_b
 	seven_seg left_digit(
 		.num(b),

Submission/Q1.txt

@@ -0,0 +1,128 @@
+// Sumbission for ELEC4720 Assignment 1 Question 1
+// Oliver Boutros (c3428958)
+// Riley King-Saunders (c3430382)
+
+`ifndef SEVEN_SEG_H_SV
+`define SEVEN_SEG_H_SV
+
+module seven_seg(
+input logic [3:0] num,          // Input binary
+input logic [0:0] rbi_inv,      // Ripple blanking input
+output logic [7:0] segments);   // segent[0] = Ripple blanking out, segment[1] to segment[7] 7 seg LEDs
+
+	always_comb begin 
+		case (num) // implement truth table as case statement
+			4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000); // zero or blank
+			4'b0001: segments = ~(8'b00001101);
+			4'b0010: segments = ~(8'b10110111);
+			4'b0011: segments = ~(8'b10011111);
+			4'b0100: segments = ~(8'b11001101);
+			4'b0101: segments = ~(8'b11011011);
+			4'b0110: segments = ~(8'b11111011);
+			4'b0111: segments = ~(8'b00001111);
+			4'b1000: segments = ~(8'b11111111);
+			4'b1001: segments = ~(8'b11001111);
+			4'b1010: segments = ~(8'b11101111);
+			4'b1011: segments = ~(8'b11111001);
+			4'b1100: segments = ~(8'b01110011);
+			4'b1101: segments = ~(8'b10111101);
+			4'b1110: segments = ~(8'b11110011);
+			4'b1111: segments = ~(8'b11100011);
+			default: segments = ~(8'bxxxxxxxx);
+		endcase     
+	end
+endmodule
+
+module seven_seg_2digit(
+input logic [3:0] b,			// left
+input logic [3:0] a,			// right
+output logic [7:0] seg_b,	// left
+output logic [7:0] seg_a); // right
+	
+	// seg_b
+	seven_seg left_digit(
+		.num(b),
+		.rbi_inv(1'b0), // blanking enabled
+		.segments(seg_b)
+	);
+	
+	// seg_a
+	seven_seg right_digit(
+		.num(a),
+		.rbi_inv(1'b1), // blanking disabled
+		.segments(seg_a)
+	);
+
+endmodule
+`endif
+
+// Testbench below
+
+module seven_seg_tb();
+    logic [3:0] in_num;
+    logic [0:0] in_rbi_inv;
+    logic [7:0] out_segments;
+    logic [7:0] true_segments[17];
+
+    seven_seg dut(in_num, in_rbi_inv, out_segments);
+
+    integer N;
+    integer i;
+    integer error_count;
+    initial begin
+
+        // Initialise truth table
+        true_segments[0 ] = ~(8'b01111111);
+        true_segments[1 ] = ~(8'b00001101);
+        true_segments[2 ] = ~(8'b10110111);
+        true_segments[3 ] = ~(8'b10011111);
+        true_segments[4 ] = ~(8'b11001101);
+        true_segments[5 ] = ~(8'b11011011);
+        true_segments[6 ] = ~(8'b11111011);
+        true_segments[7 ] = ~(8'b00001111);
+        true_segments[8 ] = ~(8'b11111111);
+        true_segments[9 ] = ~(8'b11001111);
+        true_segments[10] = ~(8'b11101111);
+        true_segments[11] = ~(8'b11111001);
+        true_segments[12] = ~(8'b01110011);
+        true_segments[13] = ~(8'b10111101);
+        true_segments[14] = ~(8'b11110011);
+        true_segments[15] = ~(8'b11100011);
+        true_segments[16] = ~(8'b00000000); // Special case for RBI
+        
+        $display("Beginning seven-segment tests");
+
+        in_num = 4'd0;
+        in_rbi_inv = 1'b0;
+        error_count = 0;
+        #1;
+        if (out_segments !== true_segments[16]) begin
+            $display("\t\x1b[38;5;9mNumber 0b%b failed to decode to 0b%b, producing 0b%b\x1b[m", in_num, true_segments[16], out_segments);
+            error_count = error_count + 1;
+        end
+        for (N=1; N < 15; ++N) begin
+            in_num = in_num + 1;
+            #1;
+            if (out_segments !== true_segments[N]) begin
+                $display("\t\x1b[38;5;9mNumber 0b%b failed to decode to 0b%b, producing 0b%b\x1b[m", in_num, true_segments[N], out_segments);
+                error_count = error_count + 1;
+            end
+        end
+
+        in_num = 4'd0;
+        in_rbi_inv = 1'b1;
+        for (N=0; N < 15; ++N) begin
+            #1;
+            if (out_segments !== true_segments[N]) begin
+                $display("\t\x1b[38;5;9mNumber 0b%b failed to decode to 0b%b, producing 0b%b\x1b[m", in_num, true_segments[N], out_segments);
+                error_count = error_count + 1;
+            end
+            in_num = in_num + 1;
+        end
+
+        if (error_count == 0) $display("\x1b[38;5;10mAll seven-segment tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d seven-segment test(s) failing\x1b[m", error_count);
+    end
+endmodule
+
+

Submission/Q2.txt

@@ -0,0 +1,84 @@
+// Sumbission for ELEC4720 Assignment 1 Question 2
+// Oliver Boutros (c3428958)
+// Riley King-Saunders (cc3430382)
+
+`ifndef LU_H_SV
+`define LU_H_SV
+module lu #(parameter width = 2) (
+    input logic [1:0] op,           // 2 bit operand
+    input logic [2**width-1:0] A,  // width defined as 2^n 
+	 input logic [2**width-1:0] B,
+    output logic [2**width-1:0] Y);
+	 
+    always_comb begin
+		case (op) // different operations of A and B based on operand
+			2'b00:	Y =   A & B;
+			2'b01:	Y =   A | B;
+			2'b10:	Y =   A ^ B;
+			2'b11:	Y = ~(A | B);
+			default:Y = '0;
+		endcase
+    end
+endmodule
+`endif
+
+// Testbench
+
+module lu_tb #(parameter W=4)();
+    logic [1:0] op;
+    logic [W-1:0] A;
+    logic [W-1:0] B;
+    logic [W-1:0] C;
+    logic [W-1:0] C_exp[16]; // expected values
+
+    lu #(W/2) dut(op, A, B, C); // width / 2 as was adapted from width-1 being standard
+
+    integer error_count;
+    initial begin // only need to check 1 bit for expected functionality
+        // AND
+        C_exp[0]  = {{W{1'b0}}, {1'b0}};
+        C_exp[1]  = {{W{1'b0}}, {1'b0}};
+        C_exp[2]  = {{W{1'b0}}, {1'b0}};
+        C_exp[3]  = {{W{1'b0}}, {1'b1}};
+        // OR
+        C_exp[4]  = {{W{1'b0}}, {1'b0}};
+        C_exp[5]  = {{W{1'b0}}, {1'b1}};
+        C_exp[6]  = {{W{1'b0}}, {1'b1}};
+        C_exp[7]  = {{W{1'b0}}, {1'b1}};
+        // XOR
+        C_exp[8]  = {{W{1'b0}}, {1'b0}};
+        C_exp[9]  = {{W{1'b0}}, {1'b1}};
+        C_exp[10] = {{W{1'b0}}, {1'b1}};
+        C_exp[11] = {{W{1'b0}}, {1'b0}};
+        // NOR
+        C_exp[12] = {{W{1'b1}}, {1'b1}};
+        C_exp[13] = {{W{1'b1}}, {1'b0}};
+        C_exp[14] = {{W{1'b1}}, {1'b0}};
+        C_exp[15] = {{W{1'b1}}, {1'b0}};
+
+        error_count = 0;
+        op = 0;
+        A = 0;
+        B = 0;
+        $display("Beginning LU tests"); // find difference between calculated and excpected
+        for (integer N = 0; N < 4; ++N) begin
+            for (integer M = 0; M < 2; ++M) begin
+                for (integer K = 0; K < 2; ++K) begin
+                    #1;
+                    if (C != C_exp[N*2*2 + M*2 + K]) begin
+                        $display("\t\x1b[38;5;9mLU(%0d) Op 0b%b(0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", N*2*2+M*2+K, op, A, B, C, C_exp[N*2*2 + M*2 + K]);
+                        error_count = error_count + 1;
+                    end
+                    B = 1;
+                end
+                A = 1;
+                B = 0;
+            end
+            A = 0;
+            B = 0;
+            op = op + 1;
+        end
+        if (error_count == 0) $display("\x1b[38;5;10mAll LU tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d LU test(s) failing\x1b[m", error_count);
+    end
+endmodule

Submission/Q3.txt

@@ -0,0 +1,190 @@
+// Sumbission for ELEC4720 Assignment 1 Question 3
+// Oliver Boutros (c3428958)
+// Riley King-Saunders (cc3430382)
+
+`ifndef ASU_H_SV
+`define ASU_H_SV
+
+`ifndef SEVEN_SEG_H_SV
+`define SEVEN_SEG_H_SV
+module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments);
+        always_comb begin
+           case (num)
+               4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000);
+               4'b0001: segments = ~(8'b00001101);
+               4'b0010: segments = ~(8'b10110111);
+               4'b0011: segments = ~(8'b10011111);
+               4'b0100: segments = ~(8'b11001101);
+               4'b0101: segments = ~(8'b11011011);
+               4'b0110: segments = ~(8'b11111011);
+               4'b0111: segments = ~(8'b00001111);
+               4'b1000: segments = ~(8'b11111111);
+               4'b1001: segments = ~(8'b11001111);
+               4'b1010: segments = ~(8'b11101111);
+               4'b1011: segments = ~(8'b11111001);
+               4'b1100: segments = ~(8'b01110011);
+               4'b1101: segments = ~(8'b10111101);
+               4'b1110: segments = ~(8'b11110011);
+               4'b1111: segments = ~(8'b11100011);
+               default: segments = ~(8'bxxxxxxxx);
+           endcase     
+        end
+endmodule
+`endif
+
+module asu #(parameter width = 2)(
+	input logic [0:0] op,
+	input logic[2**width-1:0] A, input logic[2**width-1:0] B,
+   output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN
+// Used to switch between demo mode and testbench mode
+// TODO: Strip for assignment 2
+`ifdef SYNTHESIS
+	, output logic[7:0] out_seg_1);
+`else
+    );
+`endif
+	
+    logic [2**width-1:0] operand;
+    always_comb begin
+        // A + (sub) ? B : -B
+        // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
+        //operand = (B ^ {(2**width){op}});
+        operand = op == 1'b0 ? B : ~B;
+        {COUT, OUT_1} = A + operand + {{(2**width-1){1'b0}}, op};
+    end
+
+    // Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
+    // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
+    assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
+
+	// Include seven segment visual output for hardware builds only
+    // TODO: Strip this for assignment 2 outright
+    `ifdef SYNTHESIS 
+	    seven_seg dut(OUT_1, 1'b1, out_seg_1);
+    `endif
+endmodule
+`endif
+
+
+// Testbench
+
+module asu_tb #(width=4)();
+    logic [0:0] op;
+    logic [width-1:0] A;
+    logic [width-1:0] B;
+    logic [width-1:0] C;
+    logic [0:0] Cout;
+    logic [0:0] Cin;
+    logic [width-1:0] C_exp;
+    logic [0:0] Cout_exp;
+    logic [0:0] Cin_exp;   // TODO
+
+    asu #($clog2(width)) dut(op, A, B, C, Cout, Cin);
+
+    integer error_count;
+    initial begin
+        error_count = 0;
+        $display("Beginning ASU tests");
+
+        // Test basic addition of 0+1 = 1
+        op = 1'b0;
+        A = {width{1'b0}};
+        B = { {(width-1){1'b0}}, 1'b1};
+        C_exp = { {(width-1){1'b0}}, 1'b1};
+        Cout_exp = 1'b0;
+        Cin_exp = 1'b0;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        // Test underflow from 0-1 = UINTMAX
+        op = 1'b1;
+        C_exp = {(width){1'b1}};
+        Cout_exp = 1'b0;
+        Cin_exp = 1'b0;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        // Test carry addition of 1+1 = 2
+        op = 1'b0;
+        A = { {(width-1){1'b0}}, 1'b1};
+        B = { {(width-1){1'b0}}, 1'b1};
+        C_exp = { {(width-2){1'b0}}, 2'b10};
+        Cout_exp = 1'b0;
+        Cin_exp = 1'b0;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        // Test overflow from  UINTMAX+1 = 0
+        A = {(width){1'b1}};            // UINTMAX
+        B = { {(width-1){1'b0}}, 1'b1}; // 1
+        C_exp = {(width){1'b0}};
+        Cout_exp = 1'b1;
+        Cin_exp = 1'b1;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        // Tests INTMAX+1
+        op = 1'b0;
+        A = {1'b0, {(width-1){1'b1}}};          // INTMAX
+        B = {{(width-1){1'b0}}, 1'b1};          // 1
+        C_exp    = {1'b1, {(width-1){1'b0}}};   // -INTMAX
+        Cin_exp  = 1'b1;
+        Cout_exp = 1'b0;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        op = 1'b0;
+        A = {1'b1, {(width-1){1'b0}}};  // -INTMAX
+        B = {1'b1, {(width-1){1'b0}}};  // -INTMAX
+        C_exp    = {width{1'b0}};       // 0
+        Cin_exp  = 1'b0;
+        Cout_exp = 1'b1;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        op = 1'b1;
+        A = {1'b0, {(width-1){1'b1}}}; // INTMAX
+        B = {1'b1, {(width-1){1'b0}}}; // -INTMAX
+        C_exp    = {width{1'b1}};      // -1
+        Cin_exp  = 1'b1;
+        Cout_exp = 1'b0;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        op = 1'b1;
+        A = {1'b1, {(width-1){1'b0}}};          // -INTMAX
+        B = {{(width-1){1'b0}}, 1'b1};          // 1
+        C_exp    = {1'b0, {(width-1){1'b1}}};   // INTMAX
+        Cin_exp  = 1'b0;
+        Cout_exp = 1'b1;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        if (error_count == 0) $display("\x1b[38;5;10mAll ASU tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d ASU test(s) failing\x1b[m", error_count);
+    end
+endmodule

Submission/Q4.txt

@@ -0,0 +1,357 @@
+// Sumbission for ELEC4720 Assignment 1 Question 4
+// Oliver Boutros (c3428958)
+// Riley King-Saunders (cc3430382)
+
+`ifndef ALU_H_SV
+`define ALU_H_SV
+
+`ifndef LU_H_SV
+`define LU_H_SV
+module lu #(parameter width = 2) (
+    input logic [1:0] op,           // 2 bit operand
+    input logic [2**width-1:0] A,  // width defined as 2^n 
+	 input logic [2**width-1:0] B,
+    output logic [2**width-1:0] Y);
+	 
+    always_comb begin
+		case (op) // different operations of A and B based on operand
+			2'b00:	Y =   A & B;
+			2'b01:	Y =   A | B;
+			2'b10:	Y =   A ^ B;
+			2'b11:	Y = ~(A | B);
+			default:Y = '0;
+		endcase
+    end
+endmodule
+`endif
+
+`ifndef SEVEN_SEG_H_SV
+`define SEVEN_SEG_H_SV
+module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments);
+        always_comb begin
+           case (num)
+               4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000);
+               4'b0001: segments = ~(8'b00001101);
+               4'b0010: segments = ~(8'b10110111);
+               4'b0011: segments = ~(8'b10011111);
+               4'b0100: segments = ~(8'b11001101);
+               4'b0101: segments = ~(8'b11011011);
+               4'b0110: segments = ~(8'b11111011);
+               4'b0111: segments = ~(8'b00001111);
+               4'b1000: segments = ~(8'b11111111);
+               4'b1001: segments = ~(8'b11001111);
+               4'b1010: segments = ~(8'b11101111);
+               4'b1011: segments = ~(8'b11111001);
+               4'b1100: segments = ~(8'b01110011);
+               4'b1101: segments = ~(8'b10111101);
+               4'b1110: segments = ~(8'b11110011);
+               4'b1111: segments = ~(8'b11100011);
+               default: segments = ~(8'bxxxxxxxx);
+           endcase     
+        end
+endmodule
+`endif
+
+`ifndef ASU_H_SV
+`define ASU_H_SV
+
+module asu #(parameter width = 2)(
+	input logic [0:0] op,
+	input logic[2**width-1:0] A, input logic[2**width-1:0] B,
+   output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN
+// Used to switch between demo mode and testbench mode
+// TODO: Strip for assignment 2
+`ifdef SYNTHESIS
+	, output logic[7:0] out_seg_1);
+`else
+    );
+`endif
+	
+    logic [2**width-1:0] operand;
+    always_comb begin
+        // A + (sub) ? B : -B
+        // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
+        //operand = (B ^ {(2**width){op}});
+        operand = op == 1'b0 ? B : ~B;
+        {COUT, OUT_1} = A + operand + {{(2**width-1){1'b0}}, op};
+    end
+
+    // Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
+    // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
+    assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
+
+	// Include seven segment visual output for hardware builds only
+    // TODO: Strip this for assignment 2 outright
+    `ifdef SYNTHESIS 
+	    seven_seg dut(OUT_1, 1'b1, out_seg_1);
+    `endif
+endmodule
+`endif
+
+// flags[0:0] = Cout
+// flags[1:1] = Overflow
+module alu #(parameter width=2)(input logic [3:0] op,
+    input logic [2**width-1:0] A, input logic [2**width-1:0] B,
+    output logic [2**width-1:0] OUT_1, output logic[1:0] flags
+`ifdef SYNTHESIS
+	, output logic [7:0] out_seg1);
+`else
+    );
+`endif
+    // intermediate logic for handling asu output
+    logic [0:0] asu_op;
+    logic [2**width-1:0] asu_out;
+    logic [1:0] asu_flags;
+    logic [7:0] asu_seven_seg_out;
+
+    // NOTE: For demo only
+    // TODO: Strip this for assignment 2
+    `ifdef SYNTHESIS
+        asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1], asu_seven_seg_out);
+    `else
+        asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
+    `endif
+
+    logic [2**width-1:0] lu_out;
+    lu #(width) logic_unit(op[1:0], A, B, lu_out);
+
+    always_comb begin
+        case (op) 
+            4'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
+            4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
+            4'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
+            4'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
+            4'b0100: begin OUT_1 = lu_out; flags = asu_flags; end
+            4'b0101: begin OUT_1 = lu_out; flags = asu_flags; end
+            4'b0110: begin OUT_1 = lu_out;  flags = asu_flags; end
+            4'b0111: begin OUT_1 = lu_out; flags = asu_flags; end
+            4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
+            4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
+            default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
+        endcase
+    end
+
+    // NOTE: For demo only
+    // TODO: Strip this for assignment 2
+    `ifdef SYNTHESIS
+	    seven_seg dut(OUT_1, 1'b1, out_seg1);
+    `endif
+endmodule
+`endif
+
+// Testbench
+
+module alu_tb #(width=2)();
+    localparam bitwidth = 2**width;
+
+    // Guard against future me by testing the tests
+    generate
+        if (bitwidth < 4) begin : param_asserts
+            initial begin
+                $fatal(1, "Can not instantiate an ALU testbench with less than 4 bits (n=2)");
+            end
+        end
+    endgenerate
+
+    logic [3:0] op_in;
+    logic [2**width-1:0] A_in;
+    logic [2**width-1:0] B_in;
+    logic [2**width-1:0] Y_out;
+    logic [1:0] flags_out;
+
+    localparam int NUM_TESTS = 28;
+    logic [3:0] ops[NUM_TESTS];
+    logic [2**width-1:0] A_cases[NUM_TESTS];
+    logic [2**width-1:0] B_cases[NUM_TESTS];
+    logic [2**width-1:0] Y_exp[NUM_TESTS];
+    logic [1:0] flags_exp[NUM_TESTS];
+
+    alu #(width) dut (op_in, A_in, B_in, Y_out, flags_out);
+
+    integer error_count;
+    initial begin
+        ops[0] = 4'b0000;                       // sadd
+        A_in[0] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        B_in[0] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        Y_exp[0] = {{(bitwidth-2){1'b0}}, 2'b10};  // 0
+        flags_exp[0] = {2'b00};                 // ~Cout, ~Overflow
+
+        ops[1] = 4'b0000;                       // sadd
+        A_in[1] = {bitwidth{1'b1}};                // UINTMAX
+        B_in[1] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        Y_exp[1] = {bitwidth{1'b0}};               // 0
+        flags_exp[1] = {2'b01};                 // Cout, ~Overflow
+
+        ops[2] = 4'b0000;                       // sadd
+        A_in[2] = {{1'b0}, {(bitwidth-1){1'b1}}};  // INTMAX
+        B_in[2] = {{(bitwidth-1){1'b0}} , {1'b1}}; // 1
+        Y_exp[2] = {{1'b1}, {(bitwidth-1){1'b0}} };// -INTMAX
+        flags_exp[2] = {2'b10};                 // ~Cout, Overflow
+
+        ops[3] = 4'b0000;                       // sadd
+        A_in[3] = {{1'b1}, {(bitwidth-1){1'b0}}};  // -INTMAX
+        B_in[3] = {{1'b1}, {(bitwidth-1){1'b0}}};  // -INTMAX
+        Y_exp[3] = {bitwidth{1'b0}};               // 0
+        flags_exp[3] = {2'b11};                 // Cout, Overflow
+
+        ops[4] = 4'b0001;                       // uadd
+        A_in[4] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        B_in[4] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        Y_exp[4] = {{(bitwidth-2){1'b0}}, 2'b10};  // 0
+        flags_exp[4] = {2'b00};                 // ~Cout, ~Overflow
+
+        ops[5] = 4'b0001;                       // uadd
+        A_in[5] = {bitwidth{1'b1}};                // UINTMAX
+        B_in[5] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        Y_exp[5] = {bitwidth{1'b0}};               // 0
+        flags_exp[5] = {2'b01};                 // Cout, ~Overflow
+
+        ops[6] = 4'b0001;                       // uadd
+        A_in[6] = {{1'b0}, {(bitwidth-1){1'b1}}};  // INTMAX
+        B_in[6] = {{(bitwidth-1){1'b0}} , {1'b1}}; // 1
+        Y_exp[6] = {{1'b1}, {(bitwidth-1){1'b0}} };// -INTMAX
+        flags_exp[6] = {2'b10};                 // ~Cout, Overflow
+
+        ops[7] = 4'b0001;                       // uadd
+        A_in[7] = {{1'b1}, {(bitwidth-1){1'b0}}};  // -INTMAX
+        B_in[7] = {{1'b1}, {(bitwidth-1){1'b0}}};  // -INTMAX
+        Y_exp[7] = {bitwidth{1'b0}};               // 0
+        flags_exp[7] = {2'b11};                 // Cout, Overflow
+
+        ops[8] = 4'b0010;                       // ssub
+        A_in[8] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        B_in[8] = {{(bitwidth-2){1'b0}}, 2'b10};   // 2
+        Y_exp[8] = {bitwidth{1'b1}};               // -1
+        flags_exp[8] = {2'b00};                 // ~Cout, ~Overflow
+
+        ops[9] = 4'b0010;                       // ssub
+        A_in[9] = {1'b0, {(bitwidth-1){1'b1}}};    // INTMAX
+        B_in[9] = {{(bitwidth-1){1'b0}}, 1'b1};    // -1
+        Y_exp[9] = {1'b1, {(bitwidth-1){1'b0}}};   // -INTMAX
+        flags_exp[9] = {2'b10};                 // ~Cout, Overflow
+
+        ops[10] = 4'b0010;                       // ssub
+        A_in[10] = {{(bitwidth-2){1'b0}}, 2'b10};   // 2
+        B_in[10] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        Y_exp[10] = {{(bitwidth-1){1'b0}}, 1'b1};   // 1
+        flags_exp[10] = {2'b01};                 // Cout, ~Overflow
+
+        ops[11] = 4'b0010;                       // ssub
+        A_in[11] = {1'b1, {(bitwidth-1){1'b0}}};    // -INTMAX
+        B_in[11] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        Y_exp[11] = {1'b0, {(bitwidth-1){1'b1}}};   // INTMAX
+        flags_exp[11] = {2'b11};                 // Cout, Overflow
+
+        ops[12] = 4'b0011;                       // ssub
+        A_in[12] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        B_in[12] = {{(bitwidth-2){1'b0}}, 2'b10};   // 2
+        Y_exp[12] = {bitwidth{1'b1}};               // -1
+        flags_exp[12] = {2'b00};                 // ~Cout, ~Overflow
+
+        ops[13] = 4'b0011;                       // ssub
+        A_in[13] = {1'b0, {(bitwidth-1){1'b1}}};    // INTMAX
+        B_in[13] = {{(bitwidth-1){1'b0}}, 1'b1};    // -1
+        Y_exp[13] = {1'b1, {(bitwidth-1){1'b0}}};   // -INTMAX
+        flags_exp[13] = {2'b10};                 // ~Cout, Overflow
+
+        ops[14] = 4'b0011;                       // ssub
+        A_in[14] = {{(bitwidth-2){1'b0}}, 2'b10};   // 2
+        B_in[14] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        Y_exp[14] = {{(bitwidth-1){1'b0}}, 1'b1};   // 1
+        flags_exp[14] = {2'b01};                 // Cout, ~Overflow
+
+        ops[15] = 4'b0011;                       // ssub
+        A_in[15] = {1'b1, {(bitwidth-1){1'b0}}};    // -INTMAX
+        B_in[15] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        Y_exp[15] = {1'b0, {(bitwidth-1){1'b1}}};   // INTMAX
+        flags_exp[15] = {2'b11};                 // Cout, Overflow
+
+        ops[16] = 4'b0100; // and
+        A_in[16] = {{(bitwidth-4){1'b0}}, 4'b1100};    // c
+        B_in[16] = {{(bitwidth-4){1'b0}}, 4'b1010};    // a
+        Y_exp[16] = {{(bitwidth-4){1'b0}}, 4'b1000};   // 8
+        flags_exp[16] = {2'bxx};                    // Don't care
+
+        ops[17] = 4'b0101; // or
+        A_in[17] = {{(bitwidth-4){1'b0}}, 4'b1100};    // c
+        B_in[17] = {{(bitwidth-4){1'b0}}, 4'b1010};    // a
+        Y_exp[17] = {{(bitwidth-4){1'b0}}, 4'b1110};   // e
+        flags_exp[17] = {2'bxx};                    // Don't care
+
+        ops[18] = 4'b0110; // xor
+        A_in[18] = {{(bitwidth-4){1'b0}}, 4'b1100};    // c
+        B_in[18] = {{(bitwidth-4){1'b0}}, 4'b1010};    // a
+        Y_exp[18] = {{(bitwidth-4){1'b0}}, 4'b0110};   // 6
+        flags_exp[18] = {2'bxx};                    // Don't care
+
+        ops[19] = 4'b0111; // nor
+        A_in[19] = {{(bitwidth-4){1'b0}}, 4'b1100};    // c
+        B_in[19] = {{(bitwidth-4){1'b0}}, 4'b1010};    // a
+        Y_exp[19] = {{(bitwidth-4){1'b0}}, 4'b0001};   // 1
+        flags_exp[19] = {2'bxx};                    // Don't care
+
+        ops[20] = 4'b1010;                                      // sslt: 1 < 2 (No overflow)
+        A_in[20] = {{(bitwidth-1){1'b0}}, 1'b1};                   // 1
+        B_in[20] = {{(bitwidth-2){1'b0}}, 2'b10};                  // 2
+        Y_exp[20] = {{(bitwidth-1){1'b0}}, 1'b1};                  // 1 (True)
+        flags_exp[20] = {2'b00};                                // ~Cout, ~Overflow
+
+        ops[21] = 4'b1010;                                      // sslt: 2 < 1 (No overflow)
+        A_in[21] = {{(bitwidth-2){1'b0}}, 2'b10};                  // 2
+        B_in[21] = {{(bitwidth-1){1'b0}}, 1'b1};                   // 1
+        Y_exp[21] = {bitwidth{1'b0}};                              // 0 (False)
+        flags_exp[21] = {2'b10};                                // Cout, ~Overflow
+
+        ops[22] = 4'b1010;                                      // sslt: -INTMAX < 1 (Overflow test)
+        A_in[22] = {1'b1, {(bitwidth-1){1'b0}}};                   // -INTMAX
+        B_in[22] = {{(bitwidth-1){1'b0}}, 1'b1};                   // 1
+        Y_exp[22] = {{(bitwidth-1){1'b0}}, 1'b1};                  // 1 (True)
+        flags_exp[22] = {2'b11};                                // Cout, Overflow
+
+        ops[23] = 4'b1010;                                      // sslt: INTMAX < -1 (Overflow test)
+        A_in[23] = {1'b0, {(bitwidth-1){1'b1}}};                   // INTMAX
+        B_in[23] = {bitwidth{1'b1}};                               // -1
+        Y_exp[23] = {bitwidth{1'b0}};                              // 0 (False)
+        flags_exp[23] = {2'b01};                                // ~Cout, Overflow
+
+        ops[24] = 4'b1011;                                      // uslt: 1 < 2 
+        A_in[24] = {{(bitwidth-1){1'b0}}, 1'b1};                   // 1
+        B_in[24] = {{(bitwidth-2){1'b0}}, 2'b10};                  // 2
+        Y_exp[24] = {{(bitwidth-1){1'b0}}, 1'b1};                  // 1 (True)
+        flags_exp[24] = {2'b00};                                // ~Cout, ~Overflow
+
+        ops[25] = 4'b1011;                                      // uslt: 2 < 1 
+        A_in[25] = {{(bitwidth-2){1'b0}}, 2'b10};                  // 2
+        B_in[25] = {{(bitwidth-1){1'b0}}, 1'b1};                   // 1
+        Y_exp[25] = {bitwidth{1'b0}};                              // 0 (False)
+        flags_exp[25] = {2'b10};                                // Cout, ~Overflow
+
+        ops[26] = 4'b1011;                                      // uslt: 1 < UINTMAX
+        A_in[26] = {{(bitwidth-1){1'b0}}, 1'b1};                   // 1
+        B_in[26] = {bitwidth{1'b1}};                               // UINTMAX
+        Y_exp[26] = {{(bitwidth-1){1'b0}}, 1'b1};                  // 1 (True)
+        flags_exp[26] = {2'b00};                                // ~Cout, ~Overflow
+
+        ops[27] = 4'b1011;                                      // uslt: UINTMAX < 1
+        A_in[27] = {bitwidth{1'b1}};                               // UINTMAX
+        B_in[27] = {{(bitwidth-1){1'b0}}, 1'b1};                   // 1
+        Y_exp[27] = {bitwidth{1'b0}};                              // 0 (False)
+        flags_exp[27] = {2'b10};                                // Cout, ~Overflow
+
+        error_count = 0;
+        $display("Beginning ALU tests");
+        for (integer N = 0; N < $size(ops); ++N) begin
+            op_in = ops[N];
+            A_in = A_cases[N];
+            B_in = B_cases[N];
+            #1;
+            if (Y_out != Y_exp[N]) begin
+                $display("\t\x1b[38;5;9m[%0d] ALU Instruction 0b%b produced 0b%b_%b but 0b%b_%b was expected\x1b[m", N, op_in, flags_out, Y_out, flags_exp[N], Y_exp[N]);
+                error_count = error_count + 1;
+            end
+        end
+
+        if (error_count == 0) $display("\x1b[38;5;10mAll ALU tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d ALU test(s) failing\x1b[m", error_count);
+    end
+endmodule

Submission/Q5.txt

@@ -0,0 +1,102 @@
+// Sumbission for ELEC4720 Assignment 1 Question 5
+// Oliver Boutros (c3428958)
+// Riley King-Saunders (cc3430382)
+
+`ifndef SHIFTER_H_SV
+`define SHIFTER_H_SV
+module shifter #(width=2)(input logic [2:0] op,
+    input logic[2**width-1:0] A, input logic[2**width-1:0] B, input logic[width-1:0] C, 
+    output logic[2**width-1:0] OUT_1);
+// A and B are 2^n bits wide and C is n bits wide as according to the docs
+    always_comb begin
+        case (op)
+            3'b000: OUT_1 = A << C;
+            3'b001: OUT_1 = A >> C;
+            3'b011: OUT_1 = $signed(A) >>> C;
+            3'b100: OUT_1 = A << B;
+            3'b101: OUT_1 = A >> B;
+            3'b111: OUT_1 = $signed(A) >>> B;
+            default:OUT_1 = A;
+        endcase
+    end    
+endmodule
+`endif
+
+// Testbench
+
+module shifter_tb #(width=4)();
+    logic [2:0] op;
+    logic [2**width-1:0] Y;
+    logic [2**width-1:0] A_in;
+    logic [2**width-1:0] B_in;
+    logic [width-1:0] C_in;
+
+    logic [2:0] ops[6];
+    logic [2**width-1:0] A[6];
+    logic [2**width-1:0] B[6];
+    logic [width-1:0] C[6];
+    logic [2**width-1:0] Y_exp[6];
+
+    shifter #(width) dut(op, A_in,B_in,C_in,Y);
+
+    integer error_count;
+    initial begin
+        // Test left shift by C
+        ops[0] = 3'b000;
+        A[0] = {{(2**width-1){1'b0}}, {1'b1}};
+        C[0] = {{(width-1){1'b0}}, {1'b1}};
+        B[0] = {2**width{1'b0}};
+        Y_exp[0] = {{(2**width-2){1'b0}}, {2'b10}};
+
+        // Test left shift by B
+        ops[1] = 3'b100;
+        A[1] = {{(2**width-1){1'b0}}, {1'b1}};
+        C[1] = {{(width-1){1'b0}}, {1'b1}};
+        B[1] = {{(2**width-2){1'b0}}, 2'b10};
+        Y_exp[1] = {{(2**width-3){1'b0}}, {3'b100}};
+
+        // Test Logical right shift by C
+        ops[2] = 3'b001;
+        A[2] = {{(2**width-2){1'b0}}, {2'b10}};
+        C[2] = {{(width-1){1'b0}}, {1'b1}};
+        B[2] = {2**width{1'b0}};
+        Y_exp[2] = {{(2**width-1){1'b0}}, {1'b1}};
+
+        // Test Logical right shift by B
+        ops[3] = 3'b101;
+        A[3] = {{(2**width-1){1'b0}}, {2'b10}};
+        C[3] = {{(width-1){1'b0}}, {1'b1}};
+        B[3] = {{(2**width-2){1'b0}}, 2'b10};
+        Y_exp[3] = {{(2**width-1){1'b0}}, {1'b0}};
+
+        // Test arithmetic shift right by C
+        ops[4] = 3'b011;
+        A[4] = {{(2**width-1){1'b1}}, 1'b0};   // -2
+        C[4] = {{(width-1){1'b0}}, 1'b1};   // 1
+        B[4] = {{(2**width-2){1'b0}}, 2'b10};  // 2
+        Y_exp[4] = {2**width{1'b1}};           // -1
+
+        // Test arithmetic shift right by B
+        ops[5] = 3'b111;
+        A[5] = {{(2**width-2){1'b1}}, 2'b00};   // -4
+        C[5] = {{(width-1){1'b0}}, 1'b1};   // 1
+        B[5] = {{(2**width-2){1'b0}}, 2'b10};  // 2
+        Y_exp[5] = {2**width{1'b1}};           // -1
+
+        error_count = 0;
+        $display("Beginning Shifter tests");
+        for (integer N = 0; N < $size(ops); ++N) begin
+            op = ops[N];
+            A_in = A[N];
+            B_in = B[N];
+            C_in = C[N];
+            #1;
+            if (Y != Y_exp[N]) begin
+                $display("\t\x1b[38;5;9mShifter(%0d) Op 0b%b(0b%b, 0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", N, op, A_in, B_in, C_in, Y, Y_exp[N]);
+                error_count = error_count + 1;
+            end
+        end
+        if (error_count == 0) $display("\x1b[38;5;10mAll Shifter tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d Shifter test(s) failing\x1b[m", error_count);
+    end
+endmodule

Submission/Q6.txt

@@ -0,0 +1,79 @@
+// Sumbission for ELEC4720 Assignment 1 Question 6
+// Oliver Boutros (c3428958)
+// Riley King-Saunders (cc3430382)
+
+`ifndef INSTRUCTION_CLASSIFIER_H_SV
+`define INSTRUCTION_CLASSIFIER_H_SV
+module instruction_classifier(input logic[5:0] op,
+    output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J,
+    output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F,
+    output logic[0:0] M);
+
+    always_comb begin
+        // Performs a rolling equals check
+        //  Uses an AND mask to mask off bits we don't care about
+        //  And a equals operator to perform a bitwise XNOR followed by a horizontal AND 
+        R = ( (op & 6'b111111) == 6'b000000);
+        B1= ( (op & 6'b111111) == 6'b000001);
+        J = ( (op & 6'b111110) == 6'b000010);
+        B2= ( (op & 6'b111100) == 6'b000100);
+        I = ( (op & 6'b111000) == 6'b001000);
+        F = ( (op & 6'b110000) == 6'b010000);
+        M = ( (op & 6'b100000) == 6'b100000);
+    end
+endmodule
+`endif
+
+// Testbench
+
+module instruction_classifier_tb();
+    logic [5:0] op;
+    logic [6:0] C;
+    logic [5:0] ops[12];
+    logic [6:0] C_exp[12];
+
+    instruction_classifier dut(op, C[0:0], C[1:1], C[2:2], C[3:3], C[4:4], C[5:5], C[6:6]);
+
+    integer error_count;
+    initial begin
+        ops[0] = 6'b000000;
+        C_exp[0] = 7'b0000001;
+        ops[1] = 6'b000001;
+        C_exp[1] = 7'b0000010;
+        ops[2] = 6'b000010;
+        C_exp[2] = 7'b0000100;
+        ops[3] = 6'b000100;
+        C_exp[3] = 7'b0001000;
+        ops[4] = 6'b001000;
+        C_exp[4] = 7'b0010000;
+        ops[5] = 6'b010000;
+        C_exp[5] = 7'b0100000;
+        ops[6] = 6'b100000;
+        C_exp[6] = 7'b1000000;
+
+        ops[7] = 6'b000011;
+        C_exp[7] = 7'b0000100;
+        ops[8] = 6'b000101;
+        C_exp[8] = 7'b0001000;
+        ops[9] = 6'b001001;
+        C_exp[9] = 7'b0010000;
+        ops[10] = 6'b010001;
+        C_exp[10] = 7'b0100000;
+        ops[11] = 6'b100001;
+        C_exp[11] = 7'b1000000;
+
+        error_count = 0;
+        $display("Beginning Instruction Classifier tests");
+        for (integer N = 0; N < $size(ops); ++N) begin
+            op = ops[N];
+            #1;
+            if (C != C_exp[N]) begin
+                $display("\t\x1b[38;5;9mInstruction 0b%b produced 0b%b but 0b%b was expected\x1b[m", op, C, C_exp[N]);
+                error_count = error_count + 1;
+            end
+        end
+        if (error_count == 0) $display("\x1b[38;5;10mAll Instruction Classifier tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d Instruction Classifier test(s) failing\x1b[m", error_count);
+    end
+
+endmodule

Sumbission/Q1.txt

@@ -1 +0,0 @@
-

Sumbission/Q2.txt

@@ -1 +0,0 @@
-

Sumbission/Q3.txt

@@ -1 +0,0 @@
-

Sumbission/Q4.txt

@@ -1 +0,0 @@
-

Sumbission/Q5.txt

@@ -1 +0,0 @@
-

Sumbission/Q6.txt

@@ -1 +0,0 @@
-

isv.py

@@ -0,0 +1,72 @@
+outdir = "submission"
+include_dirs = ["./modules", "./tests"]
+src_dirs = ["tests"]
+icarus_verilog_args = ["-g2012"]
+
+import argparse
+import subprocess
+from pathlib import Path
+
+parser = argparse.ArgumentParser(prog="ISV",
+                        description="A wrapper around iverilog and vvp to provide useful project utilities")
+parser.add_argument("cmd")
+
+src_files: list[Path] = []
+for src_dir in src_dirs:
+    src_dir = Path(src_dir)
+    if not (src_dir.is_file() or src_dir.is_dir()):
+        print(f"\033[38;5;9m\"{str(src_dir)}\" Is not a file or directory\033[m")
+        continue
+    src_files += [file.absolute().relative_to(Path.cwd()) for file in src_dir.rglob("*") if file.is_file()]
+
+
+def subcmd_submit(args):
+    for src_file in src_files:
+        if src_file.name == "tests.sv" or src_file.name == "tests.v":
+            continue
+
+        Path.mkdir(Path(outdir), exist_ok=True)
+        prog_args = [
+            "iverilog", *icarus_verilog_args, "-E", "-o", str(Path(outdir) / Path(src_file.name))
+        ]
+        for include_dir in include_dirs:
+            prog_args += [f"-I{include_dir}"]
+        prog_args.append(str(src_file))
+        print(prog_args)
+        subprocess.run(prog_args)
+
+def subcmd_test_submit(args):
+    test_files: list[Path] = [file for file in Path(outdir).rglob("*") if file.is_file()]
+    failed_tests = 0
+    failed_compiles = 0
+    for test_file in test_files:
+        prev_failed_compiles = failed_compiles
+        failed_compiles += int(subprocess.run(["iverilog", *icarus_verilog_args, "-o", "testbench.vvp", str(test_file)]).returncode != 0)
+        if prev_failed_compiles == failed_compiles:
+            failed_tests += int(subprocess.run(["vvp", "testbench.vvp"]).returncode != 0)
+    if failed_tests > 0 or failed_compiles > 0:
+        print(f"\033[38;5;9mFailed {failed_tests} tests with {failed_compiles} tests not compiling for submission\033[m")
+    else: print(f"\033[38;5;10mAll submission tests passing\033[m")
+
+def subcmd_test(args):
+    prog_args = [
+        "iverilog", *icarus_verilog_args, "-o", "testbench.vvp"
+    ]
+    for include_dir in include_dirs:
+        prog_args += [f"-I{include_dir}"]
+    prog_args.append("tests/tests.sv")
+    if subprocess.run(prog_args).returncode == 0:
+        assert subprocess.run(["vvp", "testbench.vvp"]).returncode == 0, "Failed to run testbench program"
+    else: print(f"\033[38;5;9mFailed to compile testbench program\033[m")
+
+subcommands = {
+    "submit": subcmd_submit,
+    "test_submit": subcmd_test_submit,
+    "test": subcmd_test
+}
+
+
+if __name__ == "__main__":
+    args = parser.parse_args()
+    assert args.cmd in subcommands, f"Invalid sub-command \"{args.cmd}\""
+    subcommands[args.cmd](args)

modules/alu.sv

@@ -9,13 +9,25 @@
 // flags[1:1] = Overflow
 module alu #(parameter width=2)(input logic [3:0] op,
     input logic [2**width-1:0] A, input logic [2**width-1:0] B,
-    output logic [2**width-1:0] OUT_1, output logic[1:0] flags,
-	 output logic [7:0] out_seg1);
-
+    output logic [2**width-1:0] OUT_1, output logic[1:0] flags
+`ifdef SYNTHESIS
+	, output logic [7:0] out_seg1);
+`else
+    );
+`endif
+    // intermediate logic for handling asu output
     logic [0:0] asu_op;
     logic [2**width-1:0] asu_out;
     logic [1:0] asu_flags;
+    logic [7:0] asu_seven_seg_out;
+
+    // NOTE: For demo only
+    // TODO: Strip this for assignment 2
+    `ifdef SYNTHESIS
+        asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1], asu_seven_seg_out);
+    `else
         asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
+    `endif
 
     logic [2**width-1:0] lu_out;
     lu #(width) logic_unit(op[1:0], A, B, lu_out);
@@ -35,6 +47,11 @@ module alu #(parameter width=2)(input logic [3:0] op,
             default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
         endcase
     end
-	 seven_seg dut(OUT_1, 1, out_seg1);
+
+    // NOTE: For demo only
+    // TODO: Strip this for assignment 2
+    `ifdef SYNTHESIS
+	    seven_seg dut(OUT_1, 1'b1, out_seg1);
+    `endif
 endmodule
 `endif

modules/asu.sv

@@ -5,8 +5,14 @@
 module asu #(parameter width = 2)(
 	input logic [0:0] op,
 	input logic[2**width-1:0] A, input logic[2**width-1:0] B,
-   output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN,
-	output logic[7:0] out_seg_1);
+   output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN
+// Used to switch between demo mode and testbench mode
+// TODO: Strip for assignment 2
+`ifdef SYNTHESIS
+	, output logic[7:0] out_seg_1);
+`else
+    );
+`endif
 	
     logic [2**width-1:0] operand;
     always_comb begin
@@ -21,6 +27,10 @@ module asu #(parameter width = 2)(
     // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
     assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
 
-	 seven_seg dut(OUT_1, 1, out_seg_1);
+	// Include seven segment visual output for hardware builds only
+    // TODO: Strip this for assignment 2 outright
+    `ifdef SYNTHESIS 
+	    seven_seg dut(OUT_1, 1'b1, out_seg_1);
+    `endif
 endmodule
 `endif

modules/lu.sv

@@ -1,13 +1,13 @@
 `ifndef LU_H_SV
 `define LU_H_SV
 module lu #(parameter width = 2) (
-    input logic [1:0] op,
-    input logic [2**width-1:0] A,
+    input logic [1:0] op,           // 2 bit operand
+    input logic [2**width-1:0] A,  // width defined as 2^n 
 	 input logic [2**width-1:0] B,
     output logic [2**width-1:0] Y);
 	 
     always_comb begin
-		case (op)
+		case (op) // different operations of A and B based on operand
 			2'b00:	Y =   A & B;
 			2'b01:	Y =   A | B;
 			2'b10:	Y =   A ^ B;

modules/shifter.sv

@@ -3,7 +3,7 @@
 module shifter #(width=2)(input logic [2:0] op,
     input logic[2**width-1:0] A, input logic[2**width-1:0] B, input logic[width-1:0] C, 
     output logic[2**width-1:0] OUT_1);
-
+// A and B are 2^n bits wide and C is n bits wide as according to the docs
     always_comb begin
         case (op)
             3'b000: OUT_1 = A << C;

tests/asu_tb.sv

@@ -1,6 +1,6 @@
 `include "asu.sv"
 
-module asu_tb #(width=8)();
+module asu_tb #(width=4)();
     logic [0:0] op;
     logic [width-1:0] A;
     logic [width-1:0] B;

tests/lu_tb.sv

@@ -5,12 +5,12 @@ module lu_tb #(parameter W=4)();
     logic [W-1:0] A;
     logic [W-1:0] B;
     logic [W-1:0] C;
-    logic [W-1:0] C_exp[16];
+    logic [W-1:0] C_exp[16]; // expected values
 
-    lu #(W/2) dut(op, A, B, C);
+    lu #(W/2) dut(op, A, B, C); // width / 2 as was adapted from width-1 being standard
 
     integer error_count;
-    initial begin
+    initial begin // only need to check 1 bit for expected functionality
         // AND
         C_exp[0]  = {{W{1'b0}}, {1'b0}};
         C_exp[1]  = {{W{1'b0}}, {1'b0}};
@@ -36,7 +36,7 @@ module lu_tb #(parameter W=4)();
         op = 0;
         A = 0;
         B = 0;
-        $display("Beginning LU tests");
+        $display("Beginning LU tests"); // find difference between calculated and excpected
         for (integer N = 0; N < 4; ++N) begin
             for (integer M = 0; M < 2; ++M) begin
                 for (integer K = 0; K < 2; ++K) begin

tests/shifter_tb.sv

@@ -1,62 +1,62 @@
 `include "shifter.sv"
-module shifter_tb #(width=8)();
+module shifter_tb #(width=4)();
     logic [2:0] op;
-    logic [width-1:0] Y;
-    logic [width-1:0] A_in;
-    logic [$clog2(width)-1:0] B_in;
+    logic [2**width-1:0] Y;
+    logic [2**width-1:0] A_in;
+    logic [2**width-1:0] B_in;
     logic [width-1:0] C_in;
 
     logic [2:0] ops[6];
-    logic [width-1:0] A[6];
-    logic [$clog2(width)-1:0] B[6];
+    logic [2**width-1:0] A[6];
+    logic [2**width-1:0] B[6];
     logic [width-1:0] C[6];
-    logic [width-1:0] Y_exp[6];
+    logic [2**width-1:0] Y_exp[6];
 
-    shifter #(width) dut(op, A_in,C_in,B_in,Y);
+    shifter #(width) dut(op, A_in,B_in,C_in,Y);
 
     integer error_count;
     initial begin
         // Test left shift by C
         ops[0] = 3'b000;
-        A[0] = {{(width-1){1'b0}}, {1'b1}};
+        A[0] = {{(2**width-1){1'b0}}, {1'b1}};
         C[0] = {{(width-1){1'b0}}, {1'b1}};
-        B[0] = {width{1'b0}};
-        Y_exp[0] = {{(width-2){1'b0}}, {2'b10}};
+        B[0] = {2**width{1'b0}};
+        Y_exp[0] = {{(2**width-2){1'b0}}, {2'b10}};
 
         // Test left shift by B
         ops[1] = 3'b100;
-        A[1] = {{(width-1){1'b0}}, {1'b1}};
+        A[1] = {{(2**width-1){1'b0}}, {1'b1}};
         C[1] = {{(width-1){1'b0}}, {1'b1}};
-        B[1] = {{($clog2(width)-2){1'b0}}, 2'b10};
-        Y_exp[1] = {{(width-3){1'b0}}, {3'b100}};
+        B[1] = {{(2**width-2){1'b0}}, 2'b10};
+        Y_exp[1] = {{(2**width-3){1'b0}}, {3'b100}};
 
         // Test Logical right shift by C
         ops[2] = 3'b001;
-        A[2] = {{(width-2){1'b0}}, {2'b10}};
+        A[2] = {{(2**width-2){1'b0}}, {2'b10}};
         C[2] = {{(width-1){1'b0}}, {1'b1}};
-        B[2] = {width{1'b0}};
-        Y_exp[2] = {{(width-1){1'b0}}, {1'b1}};
+        B[2] = {2**width{1'b0}};
+        Y_exp[2] = {{(2**width-1){1'b0}}, {1'b1}};
 
         // Test Logical right shift by B
         ops[3] = 3'b101;
-        A[3] = {{(width-1){1'b0}}, {2'b10}};
+        A[3] = {{(2**width-1){1'b0}}, {2'b10}};
         C[3] = {{(width-1){1'b0}}, {1'b1}};
-        B[3] = {{($clog2(width)-2){1'b0}}, 2'b10};
-        Y_exp[3] = {{(width-1){1'b0}}, {1'b0}};
+        B[3] = {{(2**width-2){1'b0}}, 2'b10};
+        Y_exp[3] = {{(2**width-1){1'b0}}, {1'b0}};
 
         // Test arithmetic shift right by C
         ops[4] = 3'b011;
-        A[4] = {{(width-1){1'b1}}, 1'b0};   // -2
+        A[4] = {{(2**width-1){1'b1}}, 1'b0};   // -2
         C[4] = {{(width-1){1'b0}}, 1'b1};   // 1
-        B[4] = {{(width-2){1'b0}}, 2'b10};  // 2
-        Y_exp[4] = {width{1'b1}};           // -1
+        B[4] = {{(2**width-2){1'b0}}, 2'b10};  // 2
+        Y_exp[4] = {2**width{1'b1}};           // -1
 
         // Test arithmetic shift right by B
         ops[5] = 3'b111;
-        A[5] = {{(width-2){1'b1}}, 2'b00};   // -4
+        A[5] = {{(2**width-2){1'b1}}, 2'b00};   // -4
         C[5] = {{(width-1){1'b0}}, 1'b1};   // 1
-        B[5] = {{(width-2){1'b0}}, 2'b10};  // 2
-        Y_exp[5] = {width{1'b1}};           // -1
+        B[5] = {{(2**width-2){1'b0}}, 2'b10};  // 2
+        Y_exp[5] = {2**width{1'b1}};           // -1
 
         error_count = 0;
         $display("Beginning Shifter tests");