3 Commits

Include renames

Author	SHA1	Message	Date
riley	a89a66d34d	Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage	2026-09-03 16:32:56 +10:00
riley	6668969b03	Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v	2026-09-03 16:05:52 +10:00
riley	0c21734447	Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented	2026-09-03 15:25:07 +10:00