11 Commits

Include renames

Author	SHA1	Message	Date
riley	6191f51672	Removed excess variables from hazard_unit piping. Still need to figure out what is going on with hazards_m2r_1/idex_MemRead. Also need to condense branch_taken and jump_taken into one variable.	2026-11-12 12:55:54 +11:00
riley	97f8b5b766	Fixed compile error where iverilog didn't appreciate the string parameter type.	2026-11-12 12:47:13 +11:00
riley	5ca004e1f7	Added progsrc string parameter for the hazard and nohazard testbenches to be able to specify what program to run. Added hazard unit and connected it up. Modified pipeline gate/sync registers to disable and/or reset when the hazard unit requests it. ... Modified ALU inputs to allow the hazard unit to route a just-completed calculation back around.	2026-11-12 12:36:57 +11:00
riley	2f3ecb9a3c	Updated instruction counter to have an enable/disable port	2026-11-11 15:24:41 +11:00
TroubleElectrical	d2ba06b255	Added Hazard Unit file (tested compiling correctly) labelled variables inside off of the Assignment 3 Questions PDF Figure 2. ... Also have a placeholder MUX to place before the ALU for adding hazard unit functionality	2026-11-08 12:32:40 +11:00
riley	de1f346f64	Updated assignment3 instruction counter code to be more consistent with other modules	2026-11-05 15:46:05 +11:00
TroubleElectrical	c894488c44	Fixed ByteIM.sv and removed seven seg from A3 code	2026-11-05 14:33:41 +11:00
riley	74a15cf038	Made ROM binary file configurable via a parameter. Updated assignment2 and assignment3 to reflect this. Added bit slicing in assignment2 for ram/rom addresses.	2026-11-05 14:27:01 +11:00
riley	38fa35fccd	Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module	2026-11-05 14:10:13 +11:00
riley	cc98bfbf02	Fixed compile error caused by trailing comma	2026-11-05 12:25:01 +11:00
riley	f8ea90e41d	Created assignment 3 MIPS module that uses pipelining	2026-11-04 17:28:36 +11:00