Removed excess variables from hazard_unit piping. Still need to figure out what is going on with hazards_m2r_1/idex_MemRead. Also need to condense branch_taken and jump_taken into one variable.

modules/assignment3.sv

@@ -18,7 +18,7 @@ module assignment3 #(parameter progsrc = "", parameter width=5, parameter romsz=
     logic [31:0] regs_out [32];
 
 	// Inputs
-	logic [0:0] hazard_m2r_0, hazard_m2r_1, hazard_m2r_2;
+	logic [0:0] hazard_m2r_1, hazard_m2r_2;
 	logic [0:0] hazard_reg_we_1, hazard_reg_we_2, hazard_reg_we_3;
 	logic [0:0] hazard_branch_taken, hazard_jump_taken;
 	logic [4:0] hazard_rt_0, hazard_rt_1;
@@ -29,12 +29,13 @@ module assignment3 #(parameter progsrc = "", parameter width=5, parameter romsz=
 	logic [0:0] hazard_forwardAD, hazard_forwardBD;
 	logic [0:0] hazard_stallF, hazard_stallD;
 	logic [0:0] hazard_flushE, hazard_flushD;
+	// TODO: too many variables - find what should't be here
 	hazard_unit hazard_unit(
 		hazard_m2r_1, hazard_rt_1, hazard_rs_1,
-		hazard_reg_we_1, hazard_write_reg_0, /*>Missing*/ hazard_m2r_1,
+		hazard_reg_we_1, hazard_write_reg_0, /*>Duplicate but Missing?*/ hazard_m2r_1,
 		hazard_reg_we_2, hazard_write_reg_1, /*>Missing*/ hazard_m2r_2,
 		hazard_reg_we_3, hazard_write_reg_2, // MISSING,
-		hazard_m2r_0 /* MISSING */, hazard_rs_0, hazard_rt_0,
+		hazard_rs_0, hazard_rt_0,
 		hazard_branch_taken, hazard_jump_taken,	// NOTE: We aren't doing branch prediction. Can just be control unit branch
 		hazard_forwardAE, hazard_forwardBE,
 		hazard_forwardAD, hazard_forwardBD,	// MISSING
@@ -80,7 +81,6 @@ module assignment3 #(parameter progsrc = "", parameter width=5, parameter romsz=
 	gatereg #(0, 1) gate_cu_rw_1 (clk, rst, 1'b1, cu_rw_1, cu_rw_2);
 	gatereg #(0, 1) gate_cu_rw_2 (clk, rst, 1'b1, cu_rw_2, REG_WE);
 	
-	assign hazard_m2r_0 = cu_m2r_1;
 	assign hazard_m2r_1 = cu_m2r_2;
 	assign hazard_m2r_2 = REGW_MEM_OR_RD;
 	assign hazard_reg_we_1 = cu_rw_1;