107 lines
3.8 KiB
Systemverilog
107 lines
3.8 KiB
Systemverilog
`ifndef ASS_3_SV
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`define ASS_3_SV
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`include "rom.sv"
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`include "ram.sv"
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`include "register_file.sv"
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`include "instruction_counter.sv"
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`include "control_unit.sv"
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`include "alu.sv"
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`include "shifter.sv"
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`include "sign_extender.sv"
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`include "gatereg.sv"
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`ifdef QUARTUS_SYNTH
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`include "seven_seg_4digit.sv"
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`endif
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module assignment3 #(width, romsz, ramsz)(
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input logic [0:0] clk, input logic [0:0] rst,
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`ifdef QUARTUS_SYNTH
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,
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input logic [4:0] HID_Register,
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input logic [0:0] HID_PC,
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input logic [0:0] HID_Hi_Low,
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output logic[7:0] out_seg_0,
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output logic[7:0] out_seg_1,
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output logic[7:0] out_seg_2,
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output logic[7:0] out_seg_3
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`endif
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);
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logic [2**width-1:0] pc_addr, pc_addr_2;
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logic [2**width-1:0] pc_addr_write;
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logic [0:0] pc_we;
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// TODO: Verify if we need a clk gating on pc_addr
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instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
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gatereg #(width, 2) gate_pc_addr(clk, rst, 1, pc_addr, pc_addr_2);
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logic [2**width-1:0] rom_rd;
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logic [2**width-1:0] rom_addr;
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logic [2**width-1:0] instruction, instruction_1;
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rom #(romsz, width) ROM (rom_addr, rom_rd);
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gatereg #(width, 1) gate_pc_addr(clk, rst, 1, pc_addr, rom_addr);
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gatereg #(width, 1) gate_instruction(clk, rst, 1, rom_rd, instruction);
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gatereg #(width, 1) gate_instruction_1(clk, rst, 1, instruction, instruction_1);
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logic [0:0] cu_m2r, cu_m2w, cu_b, cu_alu_src, cu_rdst, cu_rw;
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logic [3:0] cu_alu_fn, ALU_FN;
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logic [0:0] B, MEM_WE, RDST, ALU_SRC, REG_WE, REGW_MEM_OR_RD;
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control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
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cu_m2r, cu_m2w, cu_b, cu_alu_fn, cu_alu_src, cu_rdst, cu_rw
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);
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gatereg #(0, 1) gate_cu_rdst (clk, rst, 1, cu_rdst, RDST);
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gatereg #(0, 1) gate_cu_alu_src (clk, rst, 1, cu_alu_src, ALU_SRC);
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gatereg #(2, 1) gate_cu_alu_fn (clk, rst, 1, cu_alu_fn, ALU_FN);
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gatereg #(0, 2) gate_cu_b (clk, rst, 1, cu_b, B);
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gatereg #(0, 2) gate_cu_m2w (clk, rst, 1, cu_m2w, MEM_WE);
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gatereg #(0, 3) gate_cu_rw (clk, rst, 1, cu_rw, REG_WE);
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gatereg #(0, 3) gate_cu_m2r (clk, rst, 1, cu_m2r, REGW_MEM_OR_RD);
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logic [2**width-1:0] regf_rs, regf_rs_1;
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logic [2**width-1:0] regf_rt, regf_rt_1, regf_rt_2;
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logic [7:0] regf_a3, regf_a3_2;
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assign rd = (REGW_MEM_OR_RD) ? rd_mem : alu_out_2;
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assign regf_a3 = (RDST) ? instruction_1[15:11] : instruction_1[20:16];
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// TODO: Connect inputs
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gatereg #(3, 2) gate_regf_a3 (clk, rst, 1, regf_a3, regf_a3_2);
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register_file #(width, 5) REGS (
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~clk, REG_WE,
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regf_a3_2 & 8'b00011111, rd,
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instruction[25:21], regf_rs,
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instruction[20:16], regf_rt,
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regs_out
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);
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gatereg #(width, 1) gate_regf_rs(clk, rst, 1, regf_rs, regf_rs_1);
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gatereg #(width, 1) gate_regf_rt(clk, rst, 1, regf_rt, regf_rt_1);
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gatereg #(width, 1) gate_regf_rt_1(clk, rst, 1, regf_rt_1, regf_rt_2);
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logic [2**width-1:0] sign_ext_imm, rt_imm;
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sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], sign_ext_imm);
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gatereg #(width, 1) gate_sign_ext_imm(clk, rst, 1, sign_ext_imm, rt_imm);
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logic [2**width-1:0] alu_out, alu_out_1, alu_out_2;
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logic [3:0] alu_flags, alu_flags_1;
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alu #(width) ALU (ALU_FN, regf_rs_1, (ALU_SRC) ? rt_imm : regf_rt_1, rd_alu, alu_flags);
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gatereg #(width, 1) gate_alu_out (clk, rst, 1, alu_out, alu_out_1);
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gatereg #(width, 1) gate_alu_out_1 (clk, rst, 1, alu_out_1, alu_out_2);
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gatereg #(width, 1) gate_alu_flags (clk, rst, 1, alu_flags, alu_flags_1);
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logic [2**width-1:0] new_pc_addr, new_pc_addr_1;
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assign new_pc_addr = (rt_imm << 2) + pc_addr_2;
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gatereg #(width, 1) gate_new_pc_addr (clk, rst, 1, new_pc_addr, new_pc_addr_1);
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assign pc_addr_write = new_pc_addr_1;
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assign pc_we = B & alu_flags_1[2];
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logic [2**width-1:0] mem_out, mem_out_1;
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ram #(ramsz, width) RAM (clk, rst, alu_out_1, MEM_WE, regf_rt_2, mem_out);
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gatereg #(width, 1) gate_mem_out (clk, rst, 1, mem_out, mem_out_1);
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assign rd_mem = mem_out_1;
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endmodule
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`endif |