 riley
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3af4bfc875
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Added attribution to submission files
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2026-09-16 13:35:35 +10:00 |
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 TroubleElectrical
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64cd876f12
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Added attribution for submission files
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2026-09-16 13:01:43 +10:00 |
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TroubleElectrical
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cbb5bb917a
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Added Q6 submission
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2026-09-16 12:56:48 +10:00 |
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TroubleElectrical
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ae8ac98e8d
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Added Q5 comments and sumbission
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2026-09-16 12:54:18 +10:00 |
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TroubleElectrical
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13f34e62c6
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Added Q4 sumbission and comments
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2026-09-16 12:50:58 +10:00 |
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TroubleElectrical
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7d489ab77c
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Added Q3 sumbission and integrated all includes
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2026-09-16 12:42:28 +10:00 |
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TroubleElectrical
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56ade6b426
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Added comments to Logic Unit (Q2) and added to submission file
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2026-09-16 12:38:06 +10:00 |
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TroubleElectrical
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0947f26727
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Added comments to Q1 code and made submission file
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2026-09-16 10:33:08 +10:00 |
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riley
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900b544bc6
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Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken.
Renamed submission folder to fix typo.
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2026-09-15 22:00:02 +10:00 |
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