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FPGA_Uni
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7d489ab77c6bed83abd747fd3ef770d5cd54acf9
FPGA_Uni
/
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TroubleElectrical
7d489ab77c
Added Q3 sumbission and integrated all includes
2026-09-16 12:42:28 +10:00
..
Q1.txt
Added comments to Q1 code and made submission file
2026-09-16 10:33:08 +10:00
Q2.txt
Added comments to Logic Unit (Q2) and added to submission file
2026-09-16 12:38:06 +10:00
Q3.txt
Added Q3 sumbission and integrated all includes
2026-09-16 12:42:28 +10:00
Q4.txt
Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken.
2026-09-15 22:00:02 +10:00
Q5.txt
Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken.
2026-09-15 22:00:02 +10:00
Q6.txt
Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken.
2026-09-15 22:00:02 +10:00