TroubleElectrical

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Joined on 2026-09-03

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TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-13 12:04:55 +11:00

8675f5b8ee Made Assignment 2 Quartus Project

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-08 15:11:12 +11:00

b49e294b7d Updated register_file.sv with proper naming scheme and 32bit width

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-06 16:29:04 +11:00

9e3525fcac Added Byte addressable ROM from Slides

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-06 16:04:02 +11:00

3145dd6a21 Added ROM file from MIPS Architecture Slide Part 1

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-09-24 15:38:43 +10:00

179eb469c4 Removed seven segment code from alu and asu

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-09-16 13:02:23 +10:00

64cd876f12 Added attribution for submission files

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-09-16 12:57:13 +10:00

cbb5bb917a Added Q6 submission

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-09-16 12:54:54 +10:00

ae8ac98e8d Added Q5 comments and sumbission

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-09-16 12:51:31 +10:00

13f34e62c6 Added Q4 sumbission and comments

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-09-16 12:43:14 +10:00

7d489ab77c Added Q3 sumbission and integrated all includes

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-09-16 12:38:47 +10:00

56ade6b426 Added comments to Logic Unit (Q2) and added to submission file

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-09-16 10:33:51 +10:00

0947f26727 Added comments to Q1 code and made submission file

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-09-16 10:16:17 +10:00

00167dabc8 Updated ModelSim Files

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-09-15 21:10:08 +10:00

afa8d9d4db Enabled 2 segments for seven seg display decoder (Q1), most code just needs comments

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-09-15 20:02:02 +10:00

c27a04ef73 Implemented instruction classifier on board (Q6) and added blank submission files (for now)

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-09-15 19:45:26 +10:00

9583abd307 Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-09-15 19:06:38 +10:00

9d0c7011ce Updated ALU (Q4) with 7seg and confirmed operation on board

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-09-15 16:54:04 +10:00

9e5fb6f52b Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-09-15 15:17:19 +10:00

05361dcf70 Added all Testbenches to Modelsim and confirmed working operation

TroubleElectrical closed issue TroubleElectrical/FPGA_Uni#1 2026-09-10 15:26:47 +10:00

ModelSim Testbenches