Testbenches do not seem to translate directly to modelsim, some testing is required.
issue arose from me attempting to utilise / simulate the Logic Unit testbench. It does compile but the simulation complains about having no inputs in the console at the bottom and seems not to put anything on the waveform.
Testbenches do not seem to translate directly to modelsim, some testing is required.
issue arose from me attempting to utilise / simulate the Logic Unit testbench. It does compile but the simulation complains about having no inputs in the console at the bottom and seems not to put anything on the waveform.
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Testbenches do not seem to translate directly to modelsim, some testing is required.
issue arose from me attempting to utilise / simulate the Logic Unit testbench. It does compile but the simulation complains about having no inputs in the console at the bottom and seems not to put anything on the waveform.
Closing issue, just need to press F9 (or fn + F9) to make the waveform show up