TroubleElectrical

0 Followers · 0 Following

Joined on 2026-09-03

Repositories

1

Projects Packages Public Activity Starred Repositories

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-11-08 12:35:01 +11:00

d2ba06b255 Added Hazard Unit file (tested compiling correctly) labelled variables inside off of the Assignment 3 Questions PDF Figure 2.

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-11-05 14:34:34 +11:00

c894488c44 Fixed ByteIM.sv and removed seven seg from A3 code

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-11-05 14:26:10 +11:00

00b2087860 Added project to modelsim

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-22 15:54:30 +11:00

8b48084fa5 Repaired Sign extender module again to ensure only combinational logic used

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-16 15:10:34 +11:00

fb97155731 Added Assignment 2 submission zip file

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-16 14:29:28 +11:00

d962a1b557 Added code to display current PC,

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-16 13:00:45 +11:00

91a5090528 Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-16 11:33:30 +11:00

5d9e7f541e Updated RAM code to make sure Bus width is 32 bits

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-16 10:11:11 +11:00

dca673b039 Added files into modelsim folder

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-15 15:43:00 +11:00

cdde70e6c2 Updated ram.sv to resolve compilation error

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-15 15:32:38 +11:00

cd7fecd1c4 Updated code such that it will compile

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-15 15:08:38 +11:00

afb6fefe1b Updated Assignment2 with better register file module insantiation

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-15 14:52:23 +11:00

10bf499065 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

8c6765eb83 Updated reg file and assignment for compilation

Compare 2 commits »

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-15 14:35:48 +11:00

ac1062fbd5 Added Register Display Code

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-15 14:28:29 +11:00

81c05b6531 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

6bb6368f6c Added external register inspection code

Compare 2 commits »

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-13 16:57:45 +11:00

80416e1f8a TODO: Remove Shifter Code

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-13 16:35:04 +11:00

25a953cdc6 Added 4 digit 7seg display module (confirmed working for now),

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-13 15:13:25 +11:00

353923eadf Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-13 13:26:39 +11:00

19b07b649d Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

TroubleElectrical pushed to main at TroubleElectrical/FPGA_Uni 2026-10-13 12:24:29 +11:00

e57e8f362a Updated assignment 2 dependency modules (currently 8 errors in compile)