27 lines
863 B
Systemverilog
27 lines
863 B
Systemverilog
// TODO: This needs to be reworked to use manual mux-ing as to ensure low gate delay
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module instruction_classifier(input logic[5:0] op,
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output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J,
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output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F,
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output logic[0:0] M);
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always_comb begin
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logic [6:0] OUT_1;
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casez (op)
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6'b1?????: OUT_1 = 7'b1000000;
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6'b01????: OUT_1 = 7'b0100000;
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6'b001???: OUT_1 = 7'b0010000;
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6'b0001??: OUT_1 = 7'b0001000;
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6'b00001?: OUT_1 = 7'b0000100;
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6'b000001: OUT_1 = 7'b0000010;
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6'b000000: OUT_1 = 7'b0000001;
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endcase
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R = OUT_1[6];
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B1 = OUT_1[5];
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J = OUT_1[4];
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B2 = OUT_1[3];
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I = OUT_1[2];
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F = OUT_1[1];
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M = OUT_1[0];
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end
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endmodule |