// TODO: This needs to be reworked to use manual mux-ing as to ensure low gate delay
module instruction_classifier(input logic[5:0] op,
    output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J,
    output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F,
    output logic[0:0] M);

    always_comb begin
        logic [6:0] OUT_1;
        casez (op)
            6'b1?????: OUT_1 = 7'b1000000;
            6'b01????: OUT_1 = 7'b0100000;
            6'b001???: OUT_1 = 7'b0010000;
            6'b0001??: OUT_1 = 7'b0001000;
            6'b00001?: OUT_1 = 7'b0000100;
            6'b000001: OUT_1 = 7'b0000010;
            6'b000000: OUT_1 = 7'b0000001;
        endcase

        R  = OUT_1[6];
        B1 = OUT_1[5];
        J  = OUT_1[4];
        B2 = OUT_1[3];
        I  = OUT_1[2];
        F  = OUT_1[1];
        M  = OUT_1[0];
    end
endmodule