16 lines
340 B
Systemverilog
16 lines
340 B
Systemverilog
module lu #(parameter width = 2) (
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input logic [1:0] op,
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input logic [2**width-1:0] A,
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input logic [2**width-1:0] B,
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output logic [2**width-1:0] Y);
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always_comb begin
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case (op)
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2'b00: Y = A & B;
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2'b01: Y = A | B;
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2'b10: Y = A ^ B;
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2'b11: Y = ~(A | B);
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default: Y = '0;
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endcase
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end
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endmodule |