90 lines
2.3 KiB
Plaintext
90 lines
2.3 KiB
Plaintext
// Copyright (C) 2025 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and any partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, the Altera Quartus Prime License Agreement,
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// the Altera IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Altera and sold by Altera or its authorized distributors. Please
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// refer to the Altera Software License Subscription Agreements
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// on the Quartus Prime software download page.
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// VENDOR "Altera"
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// PROGRAM "Quartus Prime"
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// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"
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// DATE "10/13/2026 15:09:08"
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//
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// Device: Altera 5CGXFC5C6F27C7 Package FBGA672
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//
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//
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// This Verilog file should be used for Questa Altera FPGA (SystemVerilog) only
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//
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`timescale 1 ps/ 1 ps
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module assignment2 (
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clk);
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input logic [0:0] clk ;
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// Design Ports Information
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// clk[0] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default
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wire gnd;
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wire vcc;
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wire unknown;
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assign gnd = 1'b0;
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assign vcc = 1'b1;
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assign unknown = 1'bx;
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tri1 devclrn;
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tri1 devpor;
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tri1 devoe;
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wire \clk[0]~input_o ;
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wire \~QUARTUS_CREATED_GND~I_combout ;
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// Location: IOIBUF_X68_Y32_N61
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cyclonev_io_ibuf \clk[0]~input (
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.i(clk[0]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\clk[0]~input_o ));
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// synopsys translate_off
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defparam \clk[0]~input .bus_hold = "false";
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defparam \clk[0]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LABCELL_X9_Y53_N0
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cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
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// Equation(s):
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.dataa(gnd),
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.datab(gnd),
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.datac(gnd),
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.datad(gnd),
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.datae(gnd),
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.dataf(gnd),
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.datag(gnd),
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.cin(gnd),
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.sharein(gnd),
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.combout(\~QUARTUS_CREATED_GND~I_combout ),
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.sumout(),
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.cout(),
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.shareout());
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// synopsys translate_off
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defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
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defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
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defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
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// synopsys translate_on
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endmodule
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