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353923eadf31eb1b895f061cc6d6679e28da96e8
FPGA_Uni
/
Quartus
/
A2
/
simulation
/
questa
T
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TroubleElectrical
353923eadf
Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)
2026-10-13 15:12:00 +11:00
..
assignment2.sft
Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)
2026-10-13 13:24:44 +11:00
assignment2.svo
Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)
2026-10-13 15:12:00 +11:00