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FPGA_Uni/Quartus/A1_Q2/db/lu.hier_info

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|lu
op[0] => Mux0.IN5
op[0] => Mux1.IN5
op[0] => Mux2.IN5
op[0] => Mux3.IN5
op[1] => Mux0.IN4
op[1] => Mux1.IN4
op[1] => Mux2.IN4
op[1] => Mux3.IN4
A[0] => Y.IN0
A[0] => Y.IN0
A[0] => Y.IN0
A[1] => Y.IN0
A[1] => Y.IN0
A[1] => Y.IN0
A[2] => Y.IN0
A[2] => Y.IN0
A[2] => Y.IN0
A[3] => Y.IN0
A[3] => Y.IN0
A[3] => Y.IN0
B[0] => Y.IN1
B[0] => Y.IN1
B[0] => Y.IN1
B[1] => Y.IN1
B[1] => Y.IN1
B[1] => Y.IN1
B[2] => Y.IN1
B[2] => Y.IN1
B[2] => Y.IN1
B[3] => Y.IN1
B[3] => Y.IN1
B[3] => Y.IN1
Y[0] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
Y[1] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
Y[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
Y[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE