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FPGA_Uni
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assignment-1-submission
FPGA_Uni
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Quartus
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History
TroubleElectrical
0947f26727
Added comments to Q1 code and made submission file
2026-09-16 10:33:08 +10:00
..
A1_Q1
Added comments to Q1 code and made submission file
2026-09-16 10:33:08 +10:00
A1_Q2
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
A1_Q3
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
A1_Q4
Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)
2026-09-15 19:43:28 +10:00
A1_Q5
Implemented instruction classifier on board (Q6) and added blank submission files (for now)
2026-09-15 20:00:35 +10:00
A1_Q6
Enabled 2 segments for seven seg display decoder (Q1), most code just needs comments
2026-09-15 21:08:40 +10:00