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base: TroubleElectrical/FPGA_Uni:f8ea90e41d9796f0294345f3ef1534fa9ceed759
TroubleElectrical/FPGA_Uni:main TroubleElectrical/FPGA_Uni:assignment-1-submission
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compare: TroubleElectrical/FPGA_Uni:main
TroubleElectrical/FPGA_Uni:main TroubleElectrical/FPGA_Uni:assignment-1-submission
8 Commits
f8ea90e41d .. main
Author SHA1 Message Date
TroubleElectrical d2ba06b255 Added Hazard Unit file (tested compiling correctly) labelled variables inside off of the Assignment 3 Questions PDF Figure 2. 
Also have a placeholder MUX to place before the ALU for adding hazard unit functionality
 2026-11-08 12:32:40 +11:00
riley fe53955748 Fixed bug in test code where there was a hazzard, despite testing assuming no hazzard. Updated testbench to reflect this (Ln57-62). 
Added mem[0x000] to log message when printing registers.
Replaced 8 delay with explicit 5x 2 delays. (NOTE: Needed an extra one for ensuring write-back when comparing results.
Fixed bug where the wrong registers were being added together when creating the comparison point in the testbench.
Fixed testbench bug where S4 was checked twice and S5 not checked at all.
Updated display message on test failure to reflect that it is the pipelined version, not the single-cycle.
 2026-11-05 16:15:06 +11:00
riley de1f346f64 Updated assignment3 instruction counter code to be more consistent with other modules 2026-11-05 15:46:05 +11:00
TroubleElectrical c894488c44 Fixed ByteIM.sv and removed seven seg from A3 code 2026-11-05 14:33:41 +11:00
riley 74a15cf038 Made ROM binary file configurable via a parameter. Updated assignment2 and assignment3 to reflect this. Added bit slicing in assignment2 for ram/rom addresses. 2026-11-05 14:27:01 +11:00
TroubleElectrical 00b2087860 Added project to modelsim 2026-11-05 14:25:34 +11:00
riley 38fa35fccd Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module 2026-11-05 14:10:13 +11:00
riley cc98bfbf02 Fixed compile error caused by trailing comma 2026-11-05 12:25:01 +11:00
35 changed files with 981 additions and 377 deletions
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ModelSim/Assignment_2.cr.mti
+49 -15
View File
@@ -132,13 +132,6 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
Top level modules: Top level modules:
lu_tb lu_tb
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module sign_extender
Top level modules:
sign_extender
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module asu -- Compiling module asu
@@ -149,6 +142,27 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
Top level modules: Top level modules:
alu_tb alu_tb
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module sign_extender
Top level modules:
sign_extender
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/gatereg.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/gatereg.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module gatereg
Top level modules:
gatereg
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/hazard_unit.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/hazard_unit.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module hazard_unit
Top level modules:
hazard_unit
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module instruction_counter -- Compiling module instruction_counter
@@ -174,14 +188,6 @@ Top level modules:
rom rom
ByteIM ByteIM
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module seven_seg
-- Compiling module seven_seg_4digit
Top level modules:
seven_seg_4digit
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module instruction_classifier -- Compiling module instruction_classifier
@@ -190,6 +196,14 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
Top level modules: Top level modules:
instruction_classifier_tb instruction_classifier_tb
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module seven_seg
-- Compiling module seven_seg_4digit
Top level modules:
seven_seg_4digit
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module register_file -- Compiling module register_file
@@ -197,4 +211,24 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
Top level modules: Top level modules:
register_file register_file
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module rom
-- Compiling module ram
-- Compiling module register_file
-- Compiling module instruction_counter
-- Compiling module instruction_classifier
-- Compiling module control_unit
-- Compiling module asu
-- Compiling module lu
-- Compiling module alu
-- Compiling module shifter
-- Compiling module sign_extender
-- Compiling module gatereg
-- Compiling module assignment3
Top level modules:
shifter
assignment3
} {} {}} } {} {}}
ModelSim/Assignment_2.mpf
+35 -29
View File
@@ -410,51 +410,57 @@ ConcurrentFileLimit = 40
Project_Version = 6 Project_Version = 6
Project_DefaultLib = work Project_DefaultLib = work
Project_SortMethod = unused Project_SortMethod = unused
Project_Files_Count = 22 Project_Files_Count = 25
Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv
Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv
Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1792114203 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv Project_File_2 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv
Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv Project_File_3 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv
Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv Project_File_4 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv
Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792473740 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/control_unit.sv Project_File_5 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/control_unit.sv
Project_File_P_5 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_5 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792112234 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_6 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Project_File_6 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
Project_File_P_6 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_6 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1792115823 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv Project_File_7 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv
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Project_File_8 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv Project_File_8 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv
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Project_File_9 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv Project_File_9 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv
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Project_File_10 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv Project_File_10 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv
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Project_File_11 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv Project_File_11 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
Project_File_P_11 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1788418794 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 18 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_11 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788418794 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 18 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_12 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv Project_File_12 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
Project_File_P_12 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789513270 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_12 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789513270 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_13 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv Project_File_13 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
Project_File_P_13 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_13 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788926090 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_14 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv Project_File_14 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
Project_File_P_14 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 21 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_14 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792644107 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_15 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv Project_File_15 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
Project_File_P_15 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_15 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_16 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv Project_File_16 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/gatereg.sv
Project_File_P_16 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_16 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1793848262 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 23 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_17 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv Project_File_17 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/hazard_unit.sv
Project_File_P_17 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792113810 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_17 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1794101042 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 24 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_18 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv Project_File_18 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv
Project_File_P_18 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1792112374 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_18 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_19 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv Project_File_19 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
Project_File_P_19 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1791866874 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_19 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792115823 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_20 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv Project_File_20 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv
Project_File_P_20 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_20 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1793848949 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_21 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv Project_File_21 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
Project_File_P_21 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_21 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792119097 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_22 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
Project_File_P_22 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_23 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
Project_File_P_23 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792112234 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_24 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv
Project_File_P_24 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1793848882 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 22 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0 Project_Sim_Count = 0
Project_Folder_Count = 0 Project_Folder_Count = 0
Echo_Compile_Output = 0 Echo_Compile_Output = 0
ModelSim/alu.sv.bak
+20
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@@ -0,0 +1,20 @@
`include "asu.v"
`include "lu.v"
// flags[0:0] = Cout
// flags[1:1] = Overflow
module alu #(width=8)(input logic [3:0] op,
input logic [width-1:0] A, input logic [width-1:0] B.
output logic [width-1:0] OUT_1, output logic flags[1:0]);
logic [width-1:0] asu_out;
logic [1:0] asu_flags;
logic [0:0] asu_op;
asu #(width) adder_unit(asu_op, A, B, asu_out, asu_flags[0], asu_flags[1]);
logic [width-1:0] lu_out;
lu #(width) logic_unit(op[1:0], A, B, lu_out);
// Cout = asu_flags[0]
// Overflow = asu_flags[0] ^ asu_flags[1]
endmodule
ModelSim/assignment2.sv
+11 -3
View File
@@ -91,8 +91,15 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
`ifdef QUARTUS_SYNTH `ifdef QUARTUS_SYNTH
// Temporary Test output // Temporary Test output
// assign PC_Reg_Display = 16'hC342; // assign PC_Reg_Display = 16'hC342;
// assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0];
assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0]; always_comb begin
if (HID_PC == 1'b1) begin
PC_Reg_Display = (HID_Hi_Low) ? pc_addr[31:16] : pc_addr[15:0];
end
else begin
PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0];
end
end
seven_seg_4digit display ( seven_seg_4digit display (
.num(PC_Reg_Display), .num(PC_Reg_Display),
@@ -101,6 +108,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
.segments2(out_seg_2), .segments2(out_seg_2),
.segments3(out_seg_3) .segments3(out_seg_3)
); );
`endif `endif // code for board test outputs only
endmodule endmodule
`endif `endif
ModelSim/assignment2.sv.bak
+19
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@@ -0,0 +1,19 @@
`include "rom.sv"
`include "ram.sv"
`include "instruction_counter.sv"
`include "instruction_classifier.sv"
`include "alu.sv"
module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
logic [romsz-1:0] pc_addr;
logic [0:0] pc_we;
logic [2**width-1:0] instruction;
instruction_counter pc #(romsz)(clk, pc_we, pc_addr, pc_addr);
ROM rom #(romsz, 2**width)();
RAM ram #(ramsz, 2**width)();
alu alu #(width)();
endmodule
ModelSim/assignment3.sv
+95
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@@ -0,0 +1,95 @@
`ifndef ASS_3_SV
`define ASS_3_SV
`include "rom.sv"
`include "ram.sv"
`include "register_file.sv"
`include "instruction_counter.sv"
`include "control_unit.sv"
`include "alu.sv"
`include "shifter.sv"
`include "sign_extender.sv"
`include "gatereg.sv"
module assignment3 #(width=5, romsz=9, ramsz=10)(
input logic [0:0] clk, input logic [0:0] rst
);
logic [31:0] regs_out [32];
logic [2**width-1:0] pc_addr, pc_addr_2;
logic [2**width-1:0] pc_addr_write;
logic [0:0] pc_we;
// TODO: Verify if we need a clk gating on pc_addr
instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
gatereg #(width, 2) gate_pc_addr_1(clk, rst, 1'b1, pc_addr, pc_addr_2);
logic [2**width-1:0] rom_rd;
logic [2**width-1:0] rom_addr;
logic [2**width-1:0] instruction, instruction_1;
rom #(romsz, width) ROM (rom_addr[romsz-1:0], rom_rd);
gatereg #(width, 1) gate_pc_addr(clk, rst, 1'b1, pc_addr, rom_addr);
gatereg #(width, 1) gate_instruction(clk, rst, 1'b1, rom_rd, instruction);
gatereg #(width, 1) gate_instruction_1(clk, rst, 1'b1, instruction, instruction_1);
logic [0:0] cu_m2r, cu_m2w, cu_b, cu_alu_src, cu_rdst, cu_rw;
logic [3:0] cu_alu_fn, ALU_FN;
logic [0:0] B, MEM_WE, RDST, ALU_SRC, REG_WE, REGW_MEM_OR_RD;
control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
cu_m2r, cu_m2w, cu_b, cu_alu_fn, cu_alu_src, cu_rdst, cu_rw
);
gatereg #(0, 1) gate_cu_rdst (clk, rst, 1'b1, cu_rdst, RDST);
gatereg #(0, 1) gate_cu_alu_src (clk, rst, 1'b1, cu_alu_src, ALU_SRC);
gatereg #(2, 1) gate_cu_alu_fn (clk, rst, 1'b1, cu_alu_fn, ALU_FN);
gatereg #(0, 2) gate_cu_b (clk, rst, 1'b1, cu_b, B);
gatereg #(0, 2) gate_cu_m2w (clk, rst, 1'b1, cu_m2w, MEM_WE);
gatereg #(0, 3) gate_cu_rw (clk, rst, 1'b1, cu_rw, REG_WE);
gatereg #(0, 3) gate_cu_m2r (clk, rst, 1'b1, cu_m2r, REGW_MEM_OR_RD);
logic [2**width-1:0] regf_rs, regf_rs_1;
logic [2**width-1:0] regf_rt, regf_rt_1, regf_rt_2;
logic [7:0] regf_a3, regf_a3_2;
logic [2**width-1:0] rd, rd_mem, rd_alu;
assign rd = (REGW_MEM_OR_RD) ? rd_mem : rd_alu;
assign regf_a3 = (RDST) ? instruction_1[15:11] : instruction_1[20:16];
// TODO: Connect inputs
gatereg #(3, 2) gate_regf_a3 (clk, rst, 1'b1, regf_a3, regf_a3_2);
register_file #(width, 5) REGS (
~clk, REG_WE,
regf_a3_2[4:0], rd,
instruction[25:21], regf_rs,
instruction[20:16], regf_rt,
regs_out
);
gatereg #(width, 1) gate_regf_rs(clk, rst, 1'b1, regf_rs, regf_rs_1);
gatereg #(width, 1) gate_regf_rt(clk, rst, 1'b1, regf_rt, regf_rt_1);
gatereg #(width, 1) gate_regf_rt_1(clk, rst, 1'b1, regf_rt_1, regf_rt_2);
logic [2**width-1:0] sign_ext_imm, rt_imm;
sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], sign_ext_imm);
gatereg #(width, 1) gate_sign_ext_imm(clk, rst, 1'b1, sign_ext_imm, rt_imm);
logic [2**width-1:0] alu_out, alu_out_1, alu_out_2;
logic [3:0] alu_flags, alu_flags_1;
alu #(width) ALU (ALU_FN, regf_rs_1, (ALU_SRC) ? rt_imm : regf_rt_1, alu_out, alu_flags);
gatereg #(width, 1) gate_alu_out (clk, rst, 1'b1, alu_out, alu_out_1);
gatereg #(width, 1) gate_alu_out_1 (clk, rst, 1'b1, alu_out_1, alu_out_2);
gatereg #(width, 1) gate_alu_flags (clk, rst, 1'b1, alu_flags, alu_flags_1);
assign rd_alu = alu_out_2;
logic [2**width-1:0] new_pc_addr, new_pc_addr_1;
assign new_pc_addr = (rt_imm << 2) + pc_addr_2;
gatereg #(width, 1) gate_new_pc_addr (clk, rst, 1'b1, new_pc_addr, new_pc_addr_1);
assign pc_addr_write = new_pc_addr_1;
assign pc_we = B & alu_flags_1[2];
logic [2**width-1:0] mem_out, mem_out_1;
ram #(ramsz, width) RAM (clk, rst, alu_out_1, MEM_WE, regf_rt_2, mem_out);
gatereg #(width, 1) gate_mem_out (clk, rst, 1'b1, mem_out, mem_out_1);
assign rd_mem = mem_out_1;
endmodule
`endif
ModelSim/assignment3.sv.bak
+95
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@@ -0,0 +1,95 @@
`ifndef ASS_3_SV
`define ASS_3_SV
`include "rom.sv"
`include "ram.sv"
`include "register_file.sv"
`include "instruction_counter.sv"
`include "control_unit.sv"
`include "alu.sv"
`include "shifter.sv"
`include "sign_extender.sv"
`include "gatereg.sv"
module assignment3 #(width=5, romsz=9, ramsz=10)(
input logic [0:0] clk, input logic [0:0] rst
);
logic [31:0] regs_out [32];
logic [2**width-1:0] pc_addr, pc_addr_2;
logic [2**width-1:0] pc_addr_write;
logic [0:0] pc_we;
// TODO: Verify if we need a clk gating on pc_addr
instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
gatereg #(width, 2) gate_pc_addr_1(clk, rst, 1'b1, pc_addr, pc_addr_2);
logic [2**width-1:0] rom_rd;
logic [2**width-1:0] rom_addr;
logic [2**width-1:0] instruction, instruction_1;
rom #(romsz, width) ROM (rom_addr[romsz-1:0], rom_rd);
gatereg #(width, 1) gate_pc_addr(clk, rst, 1'b1, pc_addr, rom_addr);
gatereg #(width, 1) gate_instruction(clk, rst, 1'b1, rom_rd, instruction);
gatereg #(width, 1) gate_instruction_1(clk, rst, 1'b1, instruction, instruction_1);
logic [0:0] cu_m2r, cu_m2w, cu_b, cu_alu_src, cu_rdst, cu_rw;
logic [3:0] cu_alu_fn, ALU_FN;
logic [0:0] B, MEM_WE, RDST, ALU_SRC, REG_WE, REGW_MEM_OR_RD;
control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
cu_m2r, cu_m2w, cu_b, cu_alu_fn, cu_alu_src, cu_rdst, cu_rw
);
gatereg #(0, 1) gate_cu_rdst (clk, rst, 1'b1, cu_rdst, RDST);
gatereg #(0, 1) gate_cu_alu_src (clk, rst, 1'b1, cu_alu_src, ALU_SRC);
gatereg #(2, 1) gate_cu_alu_fn (clk, rst, 1'b1, cu_alu_fn, ALU_FN);
gatereg #(0, 2) gate_cu_b (clk, rst, 1'b1, cu_b, B);
gatereg #(0, 2) gate_cu_m2w (clk, rst, 1'b1, cu_m2w, MEM_WE);
gatereg #(0, 3) gate_cu_rw (clk, rst, 1'b1, cu_rw, REG_WE);
gatereg #(0, 3) gate_cu_m2r (clk, rst, 1'b1, cu_m2r, REGW_MEM_OR_RD);
logic [2**width-1:0] regf_rs, regf_rs_1;
logic [2**width-1:0] regf_rt, regf_rt_1, regf_rt_2;
logic [7:0] regf_a3, regf_a3_2;
logic [2**width-1:0] rd, rd_mem, rd_alu;
assign rd = (REGW_MEM_OR_RD) ? rd_mem : rd_alu;
assign regf_a3 = (RDST) ? instruction_1[15:11] : instruction_1[20:16];
// TODO: Connect inputs
gatereg #(3, 2) gate_regf_a3 (clk, rst, 1'b1, regf_a3, regf_a3_2);
register_file #(width, 5) REGS (
~clk, REG_WE,
regf_a3_2[4:0], rd,
instruction[25:21], regf_rs,
instruction[20:16], regf_rt,
regs_out
);
gatereg #(width, 1) gate_regf_rs(clk, rst, 1'b1, regf_rs, regf_rs_1);
gatereg #(width, 1) gate_regf_rt(clk, rst, 1'b1, regf_rt, regf_rt_1);
gatereg #(width, 1) gate_regf_rt_1(clk, rst, 1'b1, regf_rt_1, regf_rt_2);
logic [2**width-1:0] sign_ext_imm, rt_imm;
sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], sign_ext_imm);
gatereg #(width, 1) gate_sign_ext_imm(clk, rst, 1'b1, sign_ext_imm, rt_imm);
logic [2**width-1:0] alu_out, alu_out_1, alu_out_2;
logic [3:0] alu_flags, alu_flags_1;
alu #(width) ALU (ALU_FN, regf_rs_1, (ALU_SRC) ? rt_imm : regf_rt_1, alu_out, alu_flags);
gatereg #(width, 1) gate_alu_out (clk, rst, 1'b1, alu_out, alu_out_1);
gatereg #(width, 1) gate_alu_out_1 (clk, rst, 1'b1, alu_out_1, alu_out_2);
gatereg #(width, 1) gate_alu_flags (clk, rst, 1'b1, alu_flags, alu_flags_1);
assign rd_alu = alu_out_2;
logic [2**width-1:0] new_pc_addr, new_pc_addr_1;
assign new_pc_addr = (rt_imm << 2) + pc_addr_2;
gatereg #(width, 1) gate_new_pc_addr (clk, rst, 1'b1, new_pc_addr, new_pc_addr_1);
assign pc_addr_write = new_pc_addr_1;
assign pc_we = B & alu_flags_1[2];
logic [2**width-1:0] mem_out, mem_out_1;
ram #(ramsz, width) RAM (clk, rst, alu_out_1, MEM_WE, regf_rt_2, mem_out);
gatereg #(width, 1) gate_mem_out (clk, rst, 1'b1, mem_out, mem_out_1);
assign rd_mem = mem_out_1;
endmodule
`endif
ModelSim/asu.sv.bak
+16
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@@ -0,0 +1,16 @@
module asu #(width=8)(input logic [0:0] op,
input logic[width-1:0] A, input logic[width-1:0] B,
output logic[width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN);
logic [width-1:0] operand;
always_comb begin
// A + (sub) ? B : -B
// Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
operand = (B ^ {(width){op}});
{COUT, OUT_1} = A + operand + {{(width-1){1'b0}}, op};
end
// Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
// Cin for width-2'th bit to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
assign OUT_CIN = A[width-1] ^ operand[width-1] ^ OUT_1[width-1];
endmodule
ModelSim/gatereg.sv
+21
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@@ -0,0 +1,21 @@
module gatereg #(width, ndelay=1)(
input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] en,
input logic [2**width-1:0] in, output logic [2**width-1:0] out
);
logic [2**width-1:0] hold_value[ndelay];
assign out = hold_value[ndelay-1];
always_ff @( posedge clk ) begin
if (rst) begin
for (integer i = 0; i < ndelay; ++i) begin
hold_value[i] <= {(2**width){1'b0}};
end
end else if (en) begin
hold_value[0] <= in;
for (integer i = 1; i < ndelay; ++i) begin
hold_value[i] <= hold_value[i-1];
end
end
end
endmodule
ModelSim/hazard_unit.sv
+84
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@@ -0,0 +1,84 @@
`ifndef HAZARD_SV
`define HAZARD_SV
module hazard_unit (
// (I)Decode/EXecute stage
input logic idex_MemRead,
input logic [4:0] idex_Rt,
input logic [4:0] idex_Rs,
// EXecute/MEMory stage
input logic exmem_RegWrite,
input logic [4:0] exmem_Rd,
// MEMory/WriteBack stage
input logic memwb_RegWrite,
input logic [4:0] memwb_Rd,
// (I)Fetch/(I)Decode stage
input logic [4:0] ifid_Rs,
input logic [4:0] ifid_Rt,
// branch / jump control
input logic branch_taken,
input logic jump_taken,
// outputs
output logic [1:0] forwardA,
output logic [1:0] forwardB,
output logic stallF, // Stall OC register
output logic stallD, // Stall Instruction Memory
output logic flushE, // Flush ALU inputs
output logic flushD // Flush
);
// Forwarding encoding:
// 00 = no forwarding
// 01 = forward from MEM/WB
// 10 = forward from EX/MEM
always_comb begin
// defaults
forwardA = 2'b00;
forwardB = 2'b00;
stallF = 1'b0;
stallD = 1'b0;
flushE = 1'b0;
flushD = 1'b0;
// Forwarding for ALU src A
if (exmem_RegWrite && (exmem_Rd != 5'd0) && (exmem_Rd == idex_Rs))
forwardA = 2'b10;
else if (memwb_RegWrite && (memwb_Rd != 5'd0) && (memwb_Rd == idex_Rs))
forwardA = 2'b01;
// Forwarding for ALU src B
if (exmem_RegWrite && (exmem_Rd != 5'd0) && (exmem_Rd == idex_Rt))
forwardB = 2'b10;
else if (memwb_RegWrite && (memwb_Rd != 5'd0) && (memwb_Rd == idex_Rt))
forwardB = 2'b01;
// -------------------------
// Load-use hazard stall
// if instruction in EX is a load and
// next instruction uses its result
// -------------------------
if (idex_MemRead &&
((idex_Rt == ifid_Rs) || (idex_Rt == ifid_Rt))) begin
stallF = 1'b1;
stallD = 1'b1;
flushE = 1'b1; // insert bubble into EX
end
// -------------------------
// Control hazard flush
// branch/jump resolved in EX
// -------------------------
if (branch_taken || jump_taken) begin
flushD = 1'b1; // flush wrong instruction in decode
flushE = 1'b1; // flush wrong instruction in execute
end
end
endmodule
`endif
ModelSim/lu.sv.bak
+12
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@@ -0,0 +1,12 @@
module lu #(width=8) (
input logic [1:0] op,
input logic [width-1:0] A, input logic [width-1:0] B,
output logic [width-1:0] OUT_1);
always_comb begin
if (op == 2'b00) OUT_1 = A & B;
else if (op == 2'b01) OUT_1 = A | B;
else if (op == 2'b10) OUT_1 = A ^ B;
else if (op == 2'b10) OUT_1 = ~(A | B);
end
endmodule
ModelSim/ram.sv
+2 -2
View File
@@ -5,8 +5,8 @@ module ram #(addrwidth=9, datawidth=5)(
input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] clk, input logic [0:0] rst,
input logic [addrwidth-1:0] addr, input logic [addrwidth-1:0] addr,
input logic [0:0] we, input logic [0:0] we,
input logic [datawidth-1:0] data_in, input logic [2**datawidth-1:0] data_in,
output logic [datawidth-1:0] data_out output logic [2**datawidth-1:0] data_out
); );
// TODO: Make this byte-sized, NOT word-sized! // TODO: Make this byte-sized, NOT word-sized!
ModelSim/rom.sv
+1 -1
View File
@@ -15,7 +15,7 @@ module rom #(parameter m=7,p=4) (
`ifdef QUARTUS_SYNTH `ifdef QUARTUS_SYNTH
$readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
`else `else
$readmemh("../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary $readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
`endif `endif
end end
endmodule // end rom module endmodule // end rom module
ModelSim/seven_seg_4digit.sv
+4 -4
View File
@@ -13,28 +13,28 @@ module seven_seg_4digit (
// Rightmost digit // Rightmost digit
seven_seg digit0 ( seven_seg digit0 (
.num(num[3:0]), .num(num[3:0]),
.rbi_inv(1'b0), .rbi_inv(1'b1),
.segments(segments0) .segments(segments0)
); );
// Second digit from right // Second digit from right
seven_seg digit1 ( seven_seg digit1 (
.num(num[7:4]), .num(num[7:4]),
.rbi_inv(1'b0), .rbi_inv(1'b1),
.segments(segments1) .segments(segments1)
); );
// Third digit from right // Third digit from right
seven_seg digit2 ( seven_seg digit2 (
.num(num[11:8]), .num(num[11:8]),
.rbi_inv(1'b0), .rbi_inv(1'b1),
.segments(segments2) .segments(segments2)
); );
// Leftmost digit // Leftmost digit
seven_seg digit3 ( seven_seg digit3 (
.num(num[15:12]), .num(num[15:12]),
.rbi_inv(1'b0), .rbi_inv(1'b1),
.segments(segments3) .segments(segments3)
); );
ModelSim/shifter.sv.bak
+19
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@@ -0,0 +1,19 @@
`ifndef SHIFTER_H_SV
`define SHIFTER_H_SV
module shifter #(width=8)(input logic [2:0] op,
input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B,
output logic[width-1:0] OUT_1);
always_comb begin
case (op)
3'b000: OUT_1 = A << C;
3'b001: OUT_1 = A >> C;
3'b011: OUT_1 = $signed(A) >>> C;
3'b100: OUT_1 = A << B;
3'b101: OUT_1 = A >> B;
3'b111: OUT_1 = $signed(A) >>> B;
default:OUT_1 = A;
endcase
end
endmodule
`endif
ModelSim/sign_extender.sv
+5 -8
View File
@@ -7,13 +7,10 @@ module sign_extender #(in_width=4, out_width=5)(
output logic [2**out_width-1:0] ext_val output logic [2**out_width-1:0] ext_val
); );
logic [0:0] msb; logic [0:0] msb;
assign msb = (val & {1'b1, {(in_width-1){1'b0}}}) >> (in_width-1); assign msb = (val >> (in_width-1)) & 1'b1;
always_comb begin assign ext_val = op
if (op) begin ? { {(2**out_width - 2**in_width){msb}}, val }
ext_val = { {(2**(out_width-in_width)){msb}}, val}; : { {(2**out_width - 2**in_width){1'b0}}, val };
end else begin
ext_val = ({{(2**(out_width-in_width)){1'b0}}, val});
end
end
endmodule endmodule
`endif `endif
ModelSim/transcript
+1 -130
View File
@@ -1,131 +1,2 @@
# Loading project Assignment_2 # Loading project Assignment_2
# Compile of alu.sv was successful. # Compile of hazard_unit.sv was successful.
# Compile of alu_tb.sv was successful.
# Compile of assignment2.sv was successful.
# Compile of asu.sv was successful.
# Compile of asu_tb.sv was successful.
# Compile of ByteIM.sv was successful.
# Compile of control_unit.sv was successful.
# Compile of instruction_classifier.sv was successful.
# Compile of instruction_classifier_tb.sv was successful.
# Compile of instruction_counter.sv was successful.
# Compile of lu.sv was successful.
# Compile of lu_tb.sv was successful.
# Compile of mips.sv was successful.
# Compile of ram.sv was successful.
# Compile of register_file.sv was successful.
# Compile of rom.sv was successful.
# Compile of seven_seg.sv was successful.
# Compile of seven_seg_4digit.sv was successful.
# Compile of seven_seg_tb.sv was successful.
# Compile of shifter.sv was successful.
# Compile of shifter_tb.sv was successful.
# Compile of sign_extender.sv was successful.
# 22 compiles, 0 failed with no errors.
vsim work.mips_tb
# vsim work.mips_tb
# Start time: 12:45:51 on Oct 16,2026
# Loading sv_std.std
# Loading work.mips_tb
# Loading work.assignment2
# Loading work.instruction_counter
# Loading work.rom
# Loading work.ram
# Loading work.control_unit
# Loading work.instruction_classifier
# Loading work.register_file
# Loading work.sign_extender
# Loading work.alu
# Loading work.asu
# Loading work.lu
# ** Warning: (vsim-3015) [PCDPC] - Port size (10) does not match connection size (32) for port 'Ad'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(5).
# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM File: assignment2.sv Line: 61
# ** Warning: (vsim-3015) [PCDPC] - Port size (9) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_in'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(8).
# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_out'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(9).
# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
add wave -position end sim:/mips_tb/rst
add wave -position end sim:/mips_tb/clk
run
# ** Warning: (vsim-PLI-3408) Too few data words read on line 18 of file "../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex". Expected 1024, found 18. : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18)
# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM
run
force -freeze sim:/mips_tb/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/mips_tb/clk 1 0, 0 {10 ns} -r 20
run
quit -sim
# End time: 12:47:55 on Oct 16,2026, Elapsed time: 0:02:04
# Errors: 0, Warnings: 7
vsim work.mips_tb
# vsim work.mips_tb
# Start time: 12:47:56 on Oct 16,2026
# Loading sv_std.std
# Loading work.mips_tb
# Loading work.assignment2
# Loading work.instruction_counter
# Loading work.rom
# Loading work.ram
# Loading work.control_unit
# Loading work.instruction_classifier
# Loading work.register_file
# Loading work.sign_extender
# Loading work.alu
# Loading work.asu
# Loading work.lu
# ** Warning: (vsim-3015) [PCDPC] - Port size (10) does not match connection size (32) for port 'Ad'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(5).
# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM File: assignment2.sv Line: 61
# ** Warning: (vsim-3015) [PCDPC] - Port size (9) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_in'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(8).
# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_out'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(9).
# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
add wave -position end sim:/mips_tb/clk
add wave -position end sim:/mips_tb/rst
add wave -position end sim:/mips_tb/num_errors
force -freeze sim:/mips_tb/rst 1 0 -cancel 20
force -freeze sim:/mips_tb/clk 1 0, 0 {10 ns} -r 20
force -freeze sim:/mips_tb/clk 0 0, 1 {50 ns} -r 100
run
# ** Warning: (vsim-PLI-3408) Too few data words read on line 18 of file "../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex". Expected 1024, found 18. : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18)
# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM
add wave -position end sim:/mips_tb/CPU/regs_out
run
quit -sim
# End time: 12:50:34 on Oct 16,2026, Elapsed time: 0:02:38
# Errors: 0, Warnings: 6
vsim work.mips_tb
# vsim work.mips_tb
# Start time: 12:50:36 on Oct 16,2026
# Loading sv_std.std
# Loading work.mips_tb
# Loading work.assignment2
# Loading work.instruction_counter
# Loading work.rom
# Loading work.ram
# Loading work.control_unit
# Loading work.instruction_classifier
# Loading work.register_file
# Loading work.sign_extender
# Loading work.alu
# Loading work.asu
# Loading work.lu
# ** Warning: (vsim-3015) [PCDPC] - Port size (10) does not match connection size (32) for port 'Ad'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(5).
# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM File: assignment2.sv Line: 61
# ** Warning: (vsim-3015) [PCDPC] - Port size (9) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_in'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(8).
# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_out'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(9).
# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
add wave -position end sim:/mips_tb/clk
add wave -position end sim:/mips_tb/rst
add wave -position end sim:/mips_tb/num_errors
add wave -position end sim:/mips_tb/CPU/regs_out
run
# ** Warning: (vsim-PLI-3408) Too few data words read on line 18 of file "../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex". Expected 1024, found 18. : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18)
# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM
# End time: 12:55:34 on Oct 16,2026, Elapsed time: 0:04:58
# Errors: 0, Warnings: 6
ModelSim/work/_info
+203 -128
View File
@@ -11,32 +11,32 @@ cModel Technology
d/home/oliver/intelFPGA/20.1/modelsim_ase/bin d/home/oliver/intelFPGA/20.1/modelsim_ase/bin
valu valu
Z0 DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3 Z0 DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3
Z1 !s110 1792115142 Z1 !s110 1793848891
!i10b 1 !i10b 1
!s100 kh0:K2RRk@<XUA5?_0ad>1 !s100 KP25E<`D0[YGcmY_0OYR>3
Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1 Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1
Im?EZg:mSI^D?=D>QBY^1B0 I9jL53QmOM7UI;=OA3U@eg3
Z3 VDg1SIo80bB@j0V0VzS_@n1 Z3 VDg1SIo80bB@j0V0VzS_@n1
S1 S1
Z4 d/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim Z4 d/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim
Z5 w1792113810 Z5 w1792115823
8alu.sv 8alu.sv
Falu.sv Falu.sv
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r1 r1
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F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
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r1
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!i113 1
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R11
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Fasu.sv Fasu.sv
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r1 r1
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!i10b 1 !i10b 1
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w1792112374 w1793848949
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!i113 1 !i113 1
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R1
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R9
!i113 1
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!i113 1
R10
R11
vinstruction_classifier vinstruction_classifier
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!s107 instruction_classifier.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv| !s107 instruction_classifier.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv|
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!i113 1 !i113 1
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Flu.sv Flu.sv
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!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv| !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
!i113 1 !i113 1
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!i113 1
R10
R11
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R10 R10
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!s107 seven_seg.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv| !s107 seven_seg.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv|
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!i113 1 !i113 1
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!i113 1 !i113 1
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8shifter.sv 8shifter.sv
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31 31
R18 R7
!s107 /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv| R8
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv| R9
!i113 1 !i113 1
R10 R10
R11 R11
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asm/bin/ELEC4720-2026s2-Ass-03-NoHazardsDemo.hex
+3
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@@ -3,6 +3,9 @@
014a5023 014a5023
016b5823 016b5823
25090007 25090007
016b5823
016b5823
016b5823
ad090000 ad090000
014a5023 014a5023
016b5823 016b5823
asm/src/ELEC4720-2026s2-Ass-03-NoHazardsDemo.s
+3
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@@ -26,6 +26,9 @@ main:
subu $t2, $t2, $t2 # Set t2 = 0 subu $t2, $t2, $t2 # Set t2 = 0
subu $t3, $t3, $t3 # Set t3 = 0 subu $t3, $t3, $t3 # Set t3 = 0
addiu $t1, $t0, 7 # Set t1 = 7 (R9) addiu $t1, $t0, 7 # Set t1 = 7 (R9)
subu $t3, $t3, $t3 # Set t3 = 0
subu $t3, $t3, $t3 # Set t3 = 0
subu $t3, $t3, $t3 # Set t3 = 0
# Memory operations # Memory operations
sw $t1, 0x10000000($t0) # Save t1 to memory (change to 0x0000 for FPGA) sw $t1, 0x10000000($t0) # Save t1 to memory (change to 0x0000 for FPGA)
modules/ByteIM.sv
+1 -1
View File
@@ -10,5 +10,5 @@ module ByteIM #(parameter m=5,n=2) (
// 2**(m-n) memory words // 2**(m-n) memory words
// 2**(n+3) bit wide words // 2**(n+3) bit wide words
// Reads the whole word that contains the addressed byte // Reads the whole word that contains the addressed byte
ROM #(m-n,2**(n+3)) wordrom(Ad[m-1:n],Dout) ROM #(m-n,2**(n+3)) wordrom(Ad[m-1:n],Dout);
endmodule endmodule
modules/assignment2.sv
+7 -2
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@@ -58,10 +58,15 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr); instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
rom #(romsz, width) ROM (pc_addr, instruction); `ifdef QUARTUS_SYNTH
rom #("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", romsz, width) ROM (pc_addr[romsz-1:0], instruction);
`else
rom #("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", romsz, width) ROM (pc_addr[romsz-1:0], instruction);
`endif
logic [2**width-1:0] rd_mem; logic [2**width-1:0] rd_mem;
ram #(ramsz, width) RAM (clk, rst, rd_alu, M2W, rt, rd_mem); ram #(ramsz, width) RAM (clk, rst, rd_alu[ramsz-1:0], M2W, rt, rd_mem);
control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0], control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW
modules/assignment3.sv
+51 -45
View File
@@ -10,40 +10,28 @@
`include "shifter.sv" `include "shifter.sv"
`include "sign_extender.sv" `include "sign_extender.sv"
`include "gatereg.sv" `include "gatereg.sv"
`include "hazard_unit.sv"
`ifdef QUARTUS_SYNTH module assignment3 #(width=5, romsz=9, ramsz=10)(
`include "seven_seg_4digit.sv" input logic [0:0] clk, input logic [0:0] rst
`endif
module assignment3 #(width, romsz, ramsz)(
input logic [0:0] clk, input logic [0:0] rst,
`ifdef QUARTUS_SYNTH
,
input logic [4:0] HID_Register,
input logic [0:0] HID_PC,
input logic [0:0] HID_Hi_Low,
output logic[7:0] out_seg_0,
output logic[7:0] out_seg_1,
output logic[7:0] out_seg_2,
output logic[7:0] out_seg_3
`endif
); );
logic [2**width-1:0] pc_addr, pc_addr_2;
logic [31:0] regs_out [32];
logic [2**width-1:0] pc_addr, pc_addr_1, pc_addr_2;
logic [2**width-1:0] pc_addr_write; logic [2**width-1:0] pc_addr_write;
logic [0:0] pc_we; logic [0:0] pc_we;
// TODO: Verify if we need a clk gating on pc_addr // TODO: Verify if we need a clk gating on pc_addr
instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr); instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
gatereg #(width, 2) gate_pc_addr(clk, rst, 1, pc_addr, pc_addr_2); gatereg #(width, 1) gate_pc_addr(clk, rst, 1'b1, pc_addr, pc_addr_1);
gatereg #(width, 1) gate_pc_addr_1(clk, rst, 1'b1, pc_addr_1, pc_addr_2);
logic [2**width-1:0] rom_rd; logic [2**width-1:0] rom_rd;
logic [2**width-1:0] rom_addr;
logic [2**width-1:0] instruction, instruction_1; logic [2**width-1:0] instruction, instruction_1;
rom #(romsz, width) ROM (rom_addr, rom_rd); rom #("./asm/bin/ELEC4720-2026s2-Ass-03-NoHazardsDemo.hex", romsz, width) ROM (pc_addr_1[romsz-1:0], rom_rd);
gatereg #(width, 1) gate_pc_addr(clk, rst, 1, pc_addr, rom_addr); gatereg #(width, 1) gate_instruction(clk, rst, 1'b1, rom_rd, instruction);
gatereg #(width, 1) gate_instruction(clk, rst, 1, rom_rd, instruction); gatereg #(width, 1) gate_instruction_1(clk, rst, 1'b1, instruction, instruction_1);
gatereg #(width, 1) gate_instruction_1(clk, rst, 1, instruction, instruction_1);
logic [0:0] cu_m2r, cu_m2w, cu_b, cu_alu_src, cu_rdst, cu_rw; logic [0:0] cu_m2r, cu_m2w, cu_b, cu_alu_src, cu_rdst, cu_rw;
@@ -52,56 +40,74 @@ module assignment3 #(width, romsz, ramsz)(
control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0], control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
cu_m2r, cu_m2w, cu_b, cu_alu_fn, cu_alu_src, cu_rdst, cu_rw cu_m2r, cu_m2w, cu_b, cu_alu_fn, cu_alu_src, cu_rdst, cu_rw
); );
gatereg #(0, 1) gate_cu_rdst (clk, rst, 1, cu_rdst, RDST); gatereg #(0, 1) gate_cu_rdst (clk, rst, 1'b1, cu_rdst, RDST);
gatereg #(0, 1) gate_cu_alu_src (clk, rst, 1, cu_alu_src, ALU_SRC); gatereg #(0, 1) gate_cu_alu_src (clk, rst, 1'b1, cu_alu_src, ALU_SRC);
gatereg #(2, 1) gate_cu_alu_fn (clk, rst, 1, cu_alu_fn, ALU_FN); gatereg #(2, 1) gate_cu_alu_fn (clk, rst, 1'b1, cu_alu_fn, ALU_FN);
gatereg #(0, 2) gate_cu_b (clk, rst, 1, cu_b, B); gatereg #(0, 2) gate_cu_b (clk, rst, 1'b1, cu_b, B);
gatereg #(0, 2) gate_cu_m2w (clk, rst, 1, cu_m2w, MEM_WE); gatereg #(0, 2) gate_cu_m2w (clk, rst, 1'b1, cu_m2w, MEM_WE);
gatereg #(0, 3) gate_cu_rw (clk, rst, 1, cu_rw, REG_WE); gatereg #(0, 3) gate_cu_rw (clk, rst, 1'b1, cu_rw, REG_WE);
gatereg #(0, 3) gate_cu_m2r (clk, rst, 1, cu_m2r, REGW_MEM_OR_RD); gatereg #(0, 3) gate_cu_m2r (clk, rst, 1'b1, cu_m2r, REGW_MEM_OR_RD);
logic [2**width-1:0] regf_rs, regf_rs_1; logic [2**width-1:0] regf_rs, regf_rs_1;
logic [2**width-1:0] regf_rt, regf_rt_1, regf_rt_2; logic [2**width-1:0] regf_rt, regf_rt_1, regf_rt_2;
logic [7:0] regf_a3, regf_a3_2; logic [7:0] regf_a3, regf_a3_2;
assign rd = (REGW_MEM_OR_RD) ? rd_mem : alu_out_2; logic [2**width-1:0] rd, rd_mem, rd_alu;
assign rd = (REGW_MEM_OR_RD) ? rd_mem : rd_alu;
assign regf_a3 = (RDST) ? instruction_1[15:11] : instruction_1[20:16]; assign regf_a3 = (RDST) ? instruction_1[15:11] : instruction_1[20:16];
// TODO: Connect inputs // TODO: Connect inputs
gatereg #(3, 2) gate_regf_a3 (clk, rst, 1, regf_a3, regf_a3_2); gatereg #(3, 2) gate_regf_a3 (clk, rst, 1'b1, regf_a3, regf_a3_2);
register_file #(width, 5) REGS ( register_file #(width, 5) REGS (
~clk, REG_WE, ~clk, REG_WE,
regf_a3_2 & 8'b00011111, rd, regf_a3_2[4:0], rd,
instruction[25:21], regf_rs, instruction[25:21], regf_rs,
instruction[20:16], regf_rt, instruction[20:16], regf_rt,
regs_out regs_out
); );
gatereg #(width, 1) gate_regf_rs(clk, rst, 1, regf_rs, regf_rs_1); gatereg #(width, 1) gate_regf_rs(clk, rst, 1'b1, regf_rs, regf_rs_1);
gatereg #(width, 1) gate_regf_rt(clk, rst, 1, regf_rt, regf_rt_1); gatereg #(width, 1) gate_regf_rt(clk, rst, 1'b1, regf_rt, regf_rt_1);
gatereg #(width, 1) gate_regf_rt_1(clk, rst, 1, regf_rt_1, regf_rt_2); gatereg #(width, 1) gate_regf_rt_1(clk, rst, 1'b1, regf_rt_1, regf_rt_2);
logic [2**width-1:0] sign_ext_imm, rt_imm; logic [2**width-1:0] sign_ext_imm, rt_imm;
sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], sign_ext_imm); sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], sign_ext_imm);
gatereg #(width, 1) gate_sign_ext_imm(clk, rst, 1, sign_ext_imm, rt_imm); gatereg #(width, 1) gate_sign_ext_imm(clk, rst, 1'b1, sign_ext_imm, rt_imm);
// TODO: 3 to 1 MUX for ALU
// always_comb begin
// case (forwardA)
// 2'b00: alu_srcA = idex_readData1;
// 2'b01: alu_srcA = memwb_writedata;
// 2'b10: alu_srcA = exmem_aluout;
// default: alu_srcA = idex_readData1;
// endcase
//
// case (forwardB)
// 2'b00: alu_srcB = idex_readData2;
// 2'b01: alu_srcB = memwb_writedata;
// 2'b10: alu_srcB = exmem_aluout;
// default: alu_srcB = idex_readData2;
// endcase
// end
logic [2**width-1:0] alu_out, alu_out_1, alu_out_2; logic [2**width-1:0] alu_out, alu_out_1, alu_out_2;
logic [3:0] alu_flags, alu_flags_1; logic [3:0] alu_flags, alu_flags_1;
alu #(width) ALU (ALU_FN, regf_rs_1, (ALU_SRC) ? rt_imm : regf_rt_1, rd_alu, alu_flags); alu #(width) ALU (ALU_FN, regf_rs_1, (ALU_SRC) ? rt_imm : regf_rt_1, alu_out, alu_flags[2:0]);
gatereg #(width, 1) gate_alu_out (clk, rst, 1, alu_out, alu_out_1); gatereg #(width, 1) gate_alu_out (clk, rst, 1'b1, alu_out, alu_out_1);
gatereg #(width, 1) gate_alu_out_1 (clk, rst, 1, alu_out_1, alu_out_2); gatereg #(width, 1) gate_alu_out_1 (clk, rst, 1'b1, alu_out_1, alu_out_2);
gatereg #(width, 1) gate_alu_flags (clk, rst, 1, alu_flags, alu_flags_1); gatereg #(2, 1) gate_alu_flags (clk, rst, 1'b1, alu_flags, alu_flags_1);
assign rd_alu = alu_out_2;
logic [2**width-1:0] new_pc_addr, new_pc_addr_1; logic [2**width-1:0] new_pc_addr, new_pc_addr_1;
assign new_pc_addr = (rt_imm << 2) + pc_addr_2; assign new_pc_addr = (rt_imm << 2) + pc_addr_2;
gatereg #(width, 1) gate_new_pc_addr (clk, rst, 1, new_pc_addr, new_pc_addr_1); gatereg #(width, 1) gate_new_pc_addr (clk, rst, 1'b1, new_pc_addr, new_pc_addr_1);
assign pc_addr_write = new_pc_addr_1; assign pc_addr_write = new_pc_addr_1;
assign pc_we = B & alu_flags_1[2]; assign pc_we = B & alu_flags_1[2];
logic [2**width-1:0] mem_out, mem_out_1; logic [2**width-1:0] mem_out, mem_out_1;
ram #(ramsz, width) RAM (clk, rst, alu_out_1, MEM_WE, regf_rt_2, mem_out); ram #(ramsz, width) RAM (clk, rst, alu_out_1[ramsz-1:0], MEM_WE, regf_rt_2, mem_out);
gatereg #(width, 1) gate_mem_out (clk, rst, 1, mem_out, mem_out_1); gatereg #(width, 1) gate_mem_out (clk, rst, 1'b1, mem_out, mem_out_1);
assign rd_mem = mem_out_1; assign rd_mem = mem_out_1;
endmodule endmodule
`endif `endif
modules/gatereg.sv
+5 -3
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@@ -1,5 +1,5 @@
module gatereg #(width, ndelay=1)( module gatereg #(width, ndelay=1)(
input logic [0:0] clk, input logic [0:0] rst, input logic en[0:0], input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] en,
input logic [2**width-1:0] in, output logic [2**width-1:0] out input logic [2**width-1:0] in, output logic [2**width-1:0] out
); );
logic [2**width-1:0] hold_value[ndelay]; logic [2**width-1:0] hold_value[ndelay];
@@ -7,10 +7,12 @@ module gatereg #(width, ndelay=1)(
assign out = hold_value[ndelay-1]; assign out = hold_value[ndelay-1];
always_ff @( posedge clk ) begin always_ff @( posedge clk ) begin
if (rst) begin if (rst) begin
hold_value <= {(2**width){0}}; for (integer i = 0; i < ndelay; ++i) begin
hold_value[i] <= {(2**width){1'b0}};
end
end else if (en) begin end else if (en) begin
hold_value[0] <= in; hold_value[0] <= in;
for (int i = 1; i < ndelay; ++i) begin for (integer i = 1; i < ndelay; ++i) begin
hold_value[i] <= hold_value[i-1]; hold_value[i] <= hold_value[i-1];
end end
end end
modules/hazard_unit.sv
+79
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@@ -0,0 +1,79 @@
`ifndef HAZARD_SV
`define HAZARD_SV
module hazard_unit (
// (I)Decode/EXecute stage
input logic idex_MemRead,
input logic [4:0] idex_Rt,
input logic [4:0] idex_Rs,
// EXecute/MEMory stage
input logic exmem_RegWrite,
input logic [4:0] exmem_Rd,
// MEMory/WriteBack stage
input logic memwb_RegWrite,
input logic [4:0] memwb_Rd,
// (I)Fetch/(I)Decode stage
input logic [4:0] ifid_Rs,
input logic [4:0] ifid_Rt,
// branch / jump control
input logic branch_taken,
input logic jump_taken,
// outputs
output logic [1:0] forwardA,
output logic [1:0] forwardB,
output logic stallF, // Stall OC register
output logic stallD, // Stall Instruction Memory
output logic flushE, // Flush ALU inputs
output logic flushD // Flush
);
// Forwarding for A/B ALU inputs
// 00 = no forwarding
// 01 = forward from MEM/WB
// 10 = forward from EX/MEM
always_comb begin
// defaults
forwardA = 2'b00;
forwardB = 2'b00;
stallF = 1'b0;
stallD = 1'b0;
flushE = 1'b0;
flushD = 1'b0;
// Forwarding for ALU src A
if (exmem_RegWrite && (exmem_Rd != 5'd0) && (exmem_Rd == idex_Rs))
forwardA = 2'b10;
else if (memwb_RegWrite && (memwb_Rd != 5'd0) && (memwb_Rd == idex_Rs))
forwardA = 2'b01;
// Forwarding for ALU src B
if (exmem_RegWrite && (exmem_Rd != 5'd0) && (exmem_Rd == idex_Rt))
forwardB = 2'b10;
else if (memwb_RegWrite && (memwb_Rd != 5'd0) && (memwb_Rd == idex_Rt))
forwardB = 2'b01;
// Load-use hazard stall
// if instruction in EX is a load and next instruction uses its result
if (idex_MemRead &&
((idex_Rt == ifid_Rs) || (idex_Rt == ifid_Rt))) begin
stallF = 1'b1;
stallD = 1'b1;
flushE = 1'b1; // insert bubble into EX
end
// Control hazard flush
// branch/jump resolved in EX
if (branch_taken || jump_taken) begin
flushD = 1'b1; // flush wrong instruction in decode
flushE = 1'b1; // flush wrong instruction in execute
end
end
endmodule
`endif
modules/rom.sv
+2 -6
View File
@@ -1,7 +1,7 @@
`ifndef ROM_H `ifndef ROM_H
`define ROM_H `define ROM_H
module rom #(parameter m=7,p=4) ( module rom #(parameter string binary_path, parameter m=7,p=4) (
input logic [m-1:0] Ad, input logic [m-1:0] Ad,
output logic [2**p-1:0] Dout output logic [2**p-1:0] Dout
); );
@@ -12,11 +12,7 @@ module rom #(parameter m=7,p=4) (
//Load the program in memory //Load the program in memory
// The machine code stored in text file program.dat written in Hex format // The machine code stored in text file program.dat written in Hex format
initial begin initial begin
`ifdef QUARTUS_SYNTH $readmemh(binary_path, mem, 0, 2**m-1); //$readmemb for binary
$readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
`else
$readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
`endif
end end
endmodule // end rom module endmodule // end rom module
tests/mips_pipelined.sv
+137
View File
@@ -0,0 +1,137 @@
`include "assignment3.sv"
`timescale 1us/10ns
`define PRINT_REGISTERS(regs)\
$display("\tt0-t8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n\ts0-s8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n\tmem[0] = 0x%0x\n",\
regs[8], regs[9], regs[10], regs[11], regs[12], regs[13], regs[14], regs[15], \
regs[16], regs[17], regs[18], regs[19], regs[20], regs[21], regs[22], regs[23], \
CPU.RAM.mem[0]\
);
`define TEST_CHECK(cond) if (cond) begin end else begin \
$display("Check %s failed", `"cond`"); \
`PRINT_REGISTERS(CPU.REGS.regs); \
num_errors += 1; \
end
module mips_pipelined_tb();
logic [0:0] clk;
logic [0:0] rst;
assignment3 CPU (clk, rst);
initial clk = 0;
initial rst = 0;
always #1 clk = ~clk;
integer num_errors = 0;
initial begin
rst = 1;
#2;
rst = 0;
#2;
$dumpfile("output.vcd");
$dumpvars(0, clk);
$dumpvars(1, CPU.REGS);
$dumpvars(2, CPU.ROM);
$dumpvars(3, CPU.RAM);
$dumpvars(4, CPU.PC);
$dumpvars(5, CPU.CONTROL_UNIT);
$dumpvars(6, CPU.ALU);
$display("Beginning Pipelined MIPS tests");
#2; // 4x steps to allow pipeline to fill up
#2;
#2;
#2;
#2;
`TEST_CHECK(CPU.REGS.regs[8] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[9] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[10] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[9] == 32'd7);
#2;
`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
#2;
`TEST_CHECK(CPU.RAM.mem[0] == 32'd7);
#2;
`TEST_CHECK(CPU.REGS.regs[10] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[12] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[10] == 32'd7);
#2;
`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[12] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[13] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[11] == (CPU.REGS.regs[9] + CPU.REGS.regs[10]) );
`TEST_CHECK(CPU.REGS.regs[11] == 32'd14);
#2;
`TEST_CHECK(CPU.REGS.regs[12] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[13] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[14] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[12] == (CPU.REGS.regs[9] - CPU.REGS.regs[11]));
`TEST_CHECK(CPU.REGS.regs[12] == -32'sd7);
#2;
`TEST_CHECK(CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) );
`TEST_CHECK(CPU.REGS.regs[13] == 32'd10);
#2;
`TEST_CHECK(CPU.REGS.regs[14] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[15] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[16] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[14] == (CPU.REGS.regs[12] + CPU.REGS.regs[13]));
`TEST_CHECK(CPU.REGS.regs[14] == 32'd3);
#2;
`TEST_CHECK(CPU.REGS.regs[16] == (CPU.REGS.regs[9] & CPU.REGS.regs[13]));
`TEST_CHECK(CPU.REGS.regs[16] == 32'd2);
#2;
`TEST_CHECK(CPU.REGS.regs[17] == (CPU.REGS.regs[9] | CPU.REGS.regs[13]));
`TEST_CHECK(CPU.REGS.regs[17] == 32'd15);
#2;
`TEST_CHECK(CPU.REGS.regs[18] == (CPU.REGS.regs[9] ^ CPU.REGS.regs[13]));
`TEST_CHECK(CPU.REGS.regs[18] == 32'd13);
#2;
`TEST_CHECK(CPU.REGS.regs[19] == ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]));
`TEST_CHECK(CPU.REGS.regs[19] == 32'hfffffff0);
#2;
`TEST_CHECK(CPU.REGS.regs[20] == ( $signed(CPU.REGS.regs[12]) < $signed(CPU.REGS.regs[14]) ));
`TEST_CHECK(CPU.REGS.regs[20] == 32'd1);
#2;
`TEST_CHECK(CPU.REGS.regs[21] == ( CPU.REGS.regs[12] < CPU.REGS.regs[14] ));
`TEST_CHECK(CPU.REGS.regs[21] == 32'd0);
// TODO: Verify program never branches
#2;
#2;
#2;
#2;
// TODO: Verify final program register state
if (num_errors == 0) begin $display("\x1b[38;5;10mAll pipelined MIPS tests passing\x1b[m");
end else begin $display("\x1b[38;5;9m%0d pipelined MIPS test(s) failing\x1b[m", num_errors); end
$dumpflush;
$finish;
end
endmodule
tests/tests.sv
+1
View File
@@ -5,3 +5,4 @@
`include "tests/shifter_tb.sv" `include "tests/shifter_tb.sv"
`include "tests/alu_tb.sv" `include "tests/alu_tb.sv"
`include "tests/mips_singlecycle.sv" `include "tests/mips_singlecycle.sv"
`include "tests/mips_pipelined.sv"