6 Commits

Include renames

Author	SHA1	Message	Date
riley	de1f346f64	Updated assignment3 instruction counter code to be more consistent with other modules	2026-11-05 15:46:05 +11:00
TroubleElectrical	c894488c44	Fixed ByteIM.sv and removed seven seg from A3 code	2026-11-05 14:33:41 +11:00
riley	74a15cf038	Made ROM binary file configurable via a parameter. Updated assignment2 and assignment3 to reflect this. Added bit slicing in assignment2 for ram/rom addresses.	2026-11-05 14:27:01 +11:00
riley	38fa35fccd	Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module	2026-11-05 14:10:13 +11:00
riley	cc98bfbf02	Fixed compile error caused by trailing comma	2026-11-05 12:25:01 +11:00
riley	f8ea90e41d	Created assignment 3 MIPS module that uses pipelining	2026-11-04 17:28:36 +11:00