4 Commits

Include renames

Author	SHA1	Message	Date
riley	aee68f4664	An attempt was made to fix errors with this. There is an issue with either branching and/or register dependencies	2026-11-12 16:06:49 +11:00
riley	6b938a24be	Updated tests.sv to not perform prior module tests. Seperated testbenches for hazard and nohazard tests.	2026-11-12 12:33:24 +11:00
riley	fe53955748	Fixed bug in test code where there was a hazzard, despite testing assuming no hazzard. Updated testbench to reflect this (Ln57-62). ... Added mem[0x000] to log message when printing registers. Replaced 8 delay with explicit 5x 2 delays. (NOTE: Needed an extra one for ensuring write-back when comparing results. Fixed bug where the wrong registers were being added together when creating the comparison point in the testbench. Fixed testbench bug where S4 was checked twice and S5 not checked at all. Updated display message on test failure to reflect that it is the pipelined version, not the single-cycle.	2026-11-05 16:15:06 +11:00
riley	38fa35fccd	Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module	2026-11-05 14:10:13 +11:00