 riley
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5acf1c8b87
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Fixed bug in adder/subtracter where code assuming width was the bit width was not updated when moving to the 2**N approach required by the assignment. Updated adder/subtracter testbench to correctly instantiate the asser/subtracter and removed unused variable
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2026-09-08 22:49:22 +10:00 |
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 TroubleElectrical
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60e5dae43b
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Added ModelSim folder (and have to add files into it as to allow for different testbench code)
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2026-09-08 16:32:01 +10:00 |
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riley
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6668969b03
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Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v
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2026-09-03 16:05:52 +10:00 |
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