107 Commits

This Branch

This Branch

All Branches

Author	SHA1	Message	Date
TroubleElectrical	31a4496904	Including quartus prime lite edition project folders for flashing the project to the board	2026-09-03 16:34:31 +10:00
riley	a89a66d34d	Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage	2026-09-03 16:32:56 +10:00
riley	f881a4126b	Inverted seven segment decoder to reflect the common anode	2026-09-03 16:27:01 +10:00
riley	6668969b03	Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v	2026-09-03 16:05:52 +10:00
riley	0c21734447	Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented	2026-09-03 15:25:07 +10:00
TroubleElectrical	41252763d4	Test commit	2026-09-03 15:12:25 +10:00
TroubleElectrical	28bfe10398	Initial commit	2026-09-03 15:04:27 +10:00