6 Commits

Include renames

Author	SHA1	Message	Date
TroubleElectrical	2208eb4f16	Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.	2026-09-08 15:36:51 +10:00
riley	3e8aa911ce	Made RSIOut the LSB to correspond with wiring configuration	2026-09-03 16:56:11 +10:00
riley	dd5d044da3	Fixed bit ordering in seven segment truth table and test bench	2026-09-03 16:49:46 +10:00
riley	f881a4126b	Inverted seven segment decoder to reflect the common anode	2026-09-03 16:27:01 +10:00
riley	6668969b03	Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v	2026-09-03 16:05:52 +10:00
riley	0c21734447	Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented	2026-09-03 15:25:07 +10:00