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An attempt was made to fix errors with this. There is an issue with either branching and/or register dependencies

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riley committed 2026-11-12 16:06:49 +11:00
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commit aee68f4664
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modules/hazard_unit.sv
+38 -65
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@@ -2,78 +2,51 @@
`define HAZARD_SV
module hazard_unit (
// (I)Decode/EXecute stage
input logic idex_MemRead,
input logic [4:0] idex_Rt,
input logic [4:0] idex_Rs,
input logic [0:0] branch_decode,
input logic [4:0] rs_decode, rt_decode,
input logic [4:0] rs_execute, rt_execute,
input logic [4:0] rd_execute,
input logic [0:0] reg_write_execute, m2r_execute,
// EXecute/MEMory stage
input logic exmem_RegWrite,
input logic [4:0] exmem_Rd,
input logic [4:0] rd_memory,
input logic [0:0] reg_write_memory, m2r_memory,
// MEMory/WriteBack stage
input logic memwb_RegWrite,
input logic [4:0] memwb_Rd,
input logic [4:0] rd_writeback,
input logic [0:0] reg_write_writeback,
// (I)Fetch/(I)Decode stage
input logic [4:0] ifid_Rs,
input logic [4:0] ifid_Rt,
// branch / jump control
input logic branch_taken,
input logic jump_taken,
// outputs
output logic [1:0] forwardA,
output logic [1:0] forwardB,
output logic stallF, // Stall OC register
output logic stallD, // Stall Instruction Memory
output logic flushE, // Flush ALU inputs
output logic flushD // Flush
output logic [0:0] stall_fetch, stall_decode,
output logic [0:0] forward_a_decode, forward_b_decode,
output logic [0:0] flush_execute,
output logic [1:0] forward_a_execute, forward_b_execute
);
// Forwarding for A/B ALU inputs
// 00 = no forwarding
// 01 = forward from MEM/WB
// 10 = forward from EX/MEM
always_comb begin
// defaults
forwardA = 2'b00;
forwardB = 2'b00;
stallF = 1'b0;
stallD = 1'b0;
flushE = 1'b0;
flushD = 1'b0;
forward_a_execute = 2'b00;
forward_b_execute = 2'b00;
// Forwarding for ALU src A
if (exmem_RegWrite && (exmem_Rd != 5'd0) && (exmem_Rd == idex_Rs))
forwardA = 2'b10;
else if (memwb_RegWrite && (memwb_Rd != 5'd0) && (memwb_Rd == idex_Rs))
forwardA = 2'b01;
// Forwarding for ALU src B
if (exmem_RegWrite && (exmem_Rd != 5'd0) && (exmem_Rd == idex_Rt))
forwardB = 2'b10;
else if (memwb_RegWrite && (memwb_Rd != 5'd0) && (memwb_Rd == idex_Rt))
forwardB = 2'b01;
// Load-use hazard stall
// if instruction in EX is a load and next instruction uses its result
if (idex_MemRead &&
((idex_Rt == ifid_Rs) || (idex_Rt == ifid_Rt))) begin
stallF = 1'b1;
stallD = 1'b1;
flushE = 1'b1; // insert bubble into EX
end
// Control hazard flush
// branch/jump resolved in EX
if (branch_taken || jump_taken) begin
flushD = 1'b1; // flush wrong instruction in decode
flushE = 1'b1; // flush wrong instruction in execute
end
if ( (rs_execute != 5'd0) && (rs_execute == rd_memory) && reg_write_memory)
forward_a_execute = 2'b10;
else if ( (rs_execute != 5'd0) && (rs_execute == rd_memory) && reg_write_writeback)
forward_a_execute = 2'b01;
if ( (rt_execute != 5'd0) && (rt_execute == rd_memory) && reg_write_memory)
forward_b_execute = 2'b10;
else if ( (rt_execute != 5'd0) && (rt_execute == rd_memory) && reg_write_writeback)
forward_b_execute = 2'b01;
end
logic [0:0] loaduse_stall;
assign loaduse_stall = ((rs_decode == rt_execute) | (rt_decode == rt_execute)) & m2r_execute;
assign forward_a_decode = (rs_decode != 5'd0) & (rs_decode == rd_memory) & reg_write_memory;
assign forward_b_decode = (rt_decode != 5'd0) & (rt_decode == rd_memory) & reg_write_memory;
logic [0:0] branch_stall;
assign branch_stall = (branch_decode & reg_write_execute & (rd_execute == rs_decode || rd_execute == rt_decode) ) ||
(branch_decode & m2r_memory & (rd_memory == rs_decode || rd_memory == rt_decode) );
assign stall_fetch = loaduse_stall | branch_stall;
assign stall_decode = loaduse_stall | branch_stall;
assign flush_execute = loaduse_stall | branch_stall;
endmodule
`endif