53 lines
2.0 KiB
Systemverilog
53 lines
2.0 KiB
Systemverilog
`ifndef HAZARD_SV
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`define HAZARD_SV
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module hazard_unit (
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input logic [0:0] branch_decode,
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input logic [4:0] rs_decode, rt_decode,
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input logic [4:0] rs_execute, rt_execute,
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input logic [4:0] rd_execute,
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input logic [0:0] reg_write_execute, m2r_execute,
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input logic [4:0] rd_memory,
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input logic [0:0] reg_write_memory, m2r_memory,
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input logic [4:0] rd_writeback,
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input logic [0:0] reg_write_writeback,
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output logic [0:0] stall_fetch, stall_decode,
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output logic [0:0] forward_a_decode, forward_b_decode,
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output logic [0:0] flush_execute,
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output logic [1:0] forward_a_execute, forward_b_execute
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);
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always_comb begin
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forward_a_execute = 2'b00;
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forward_b_execute = 2'b00;
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if ( (rs_execute != 5'd0) && (rs_execute == rd_memory) && reg_write_memory)
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forward_a_execute = 2'b10;
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else if ( (rs_execute != 5'd0) && (rs_execute == rd_memory) && reg_write_writeback)
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forward_a_execute = 2'b01;
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if ( (rt_execute != 5'd0) && (rt_execute == rd_memory) && reg_write_memory)
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forward_b_execute = 2'b10;
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else if ( (rt_execute != 5'd0) && (rt_execute == rd_memory) && reg_write_writeback)
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forward_b_execute = 2'b01;
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end
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logic [0:0] loaduse_stall;
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assign loaduse_stall = ((rs_decode == rt_execute) | (rt_decode == rt_execute)) & m2r_execute;
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assign forward_a_decode = (rs_decode != 5'd0) & (rs_decode == rd_memory) & reg_write_memory;
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assign forward_b_decode = (rt_decode != 5'd0) & (rt_decode == rd_memory) & reg_write_memory;
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logic [0:0] branch_stall;
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assign branch_stall = (branch_decode & reg_write_execute & (rd_execute == rs_decode || rd_execute == rt_decode) ) ||
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(branch_decode & m2r_memory & (rd_memory == rs_decode || rd_memory == rt_decode) );
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assign stall_fetch = loaduse_stall | branch_stall;
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assign stall_decode = loaduse_stall | branch_stall;
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assign flush_execute = loaduse_stall | branch_stall;
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endmodule
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`endif
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