From 6668969b033a06a6e1cfe7510dc04319e4a6b59e Mon Sep 17 00:00:00 2001
From: Riley King-Saunders <riley.kingsaunders@gmail.com>
Date: Thu, 3 Sep 2026 16:05:52 +1000
Subject: [PATCH] Made it clear that we are using SystemVerilog by renaming HDL
 files to end in .sv rather than .v

---
 modules/{alu.v => alu.sv}                                         | 0
 modules/{asu.v => asu.sv}                                         | 0
 modules/{instruction_classifier.v => instruction_classifier.sv}   | 0
 modules/{lu.v => lu.sv}                                           | 0
 modules/{seven_seg.v => seven_seg.sv}                             | 0
 modules/{shifter.v => shifter.sv}                                 | 0
 tests/{alu_tb.v => alu_tb.sv}                                     | 0
 tests/{asu_tb.v => asu_tb.sv}                                     | 0
 .../{instruction_classifier_tb.v => instruction_classifier_tb.sv} | 0
 tests/{lu_tb.v => lu_tb.sv}                                       | 0
 tests/{seven_seg_tb.v => seven_seg_tb.sv}                         | 0
 tests/{shifter_tb.v => shifter_tb.sv}                             | 0
 tests/{tests.v => tests.sv}                                       | 0
 13 files changed, 0 insertions(+), 0 deletions(-)
 rename modules/{alu.v => alu.sv} (100%)
 rename modules/{asu.v => asu.sv} (100%)
 rename modules/{instruction_classifier.v => instruction_classifier.sv} (100%)
 rename modules/{lu.v => lu.sv} (100%)
 rename modules/{seven_seg.v => seven_seg.sv} (100%)
 rename modules/{shifter.v => shifter.sv} (100%)
 rename tests/{alu_tb.v => alu_tb.sv} (100%)
 rename tests/{asu_tb.v => asu_tb.sv} (100%)
 rename tests/{instruction_classifier_tb.v => instruction_classifier_tb.sv} (100%)
 rename tests/{lu_tb.v => lu_tb.sv} (100%)
 rename tests/{seven_seg_tb.v => seven_seg_tb.sv} (100%)
 rename tests/{shifter_tb.v => shifter_tb.sv} (100%)
 rename tests/{tests.v => tests.sv} (100%)

diff --git a/modules/alu.v b/modules/alu.sv
similarity index 100%
rename from modules/alu.v
rename to modules/alu.sv
diff --git a/modules/asu.v b/modules/asu.sv
similarity index 100%
rename from modules/asu.v
rename to modules/asu.sv
diff --git a/modules/instruction_classifier.v b/modules/instruction_classifier.sv
similarity index 100%
rename from modules/instruction_classifier.v
rename to modules/instruction_classifier.sv
diff --git a/modules/lu.v b/modules/lu.sv
similarity index 100%
rename from modules/lu.v
rename to modules/lu.sv
diff --git a/modules/seven_seg.v b/modules/seven_seg.sv
similarity index 100%
rename from modules/seven_seg.v
rename to modules/seven_seg.sv
diff --git a/modules/shifter.v b/modules/shifter.sv
similarity index 100%
rename from modules/shifter.v
rename to modules/shifter.sv
diff --git a/tests/alu_tb.v b/tests/alu_tb.sv
similarity index 100%
rename from tests/alu_tb.v
rename to tests/alu_tb.sv
diff --git a/tests/asu_tb.v b/tests/asu_tb.sv
similarity index 100%
rename from tests/asu_tb.v
rename to tests/asu_tb.sv
diff --git a/tests/instruction_classifier_tb.v b/tests/instruction_classifier_tb.sv
similarity index 100%
rename from tests/instruction_classifier_tb.v
rename to tests/instruction_classifier_tb.sv
diff --git a/tests/lu_tb.v b/tests/lu_tb.sv
similarity index 100%
rename from tests/lu_tb.v
rename to tests/lu_tb.sv
diff --git a/tests/seven_seg_tb.v b/tests/seven_seg_tb.sv
similarity index 100%
rename from tests/seven_seg_tb.v
rename to tests/seven_seg_tb.sv
diff --git a/tests/shifter_tb.v b/tests/shifter_tb.sv
similarity index 100%
rename from tests/shifter_tb.v
rename to tests/shifter_tb.sv
diff --git a/tests/tests.v b/tests/tests.sv
similarity index 100%
rename from tests/tests.v
rename to tests/tests.sv