FPGA_Uni/tests/instruction_classifier_tb.sv at 6668969b033a06a6e1cfe7510dc04319e4a6b59e - FPGA_Uni - Riley's Git Server

TroubleElectrical/FPGA_Uni

0 Fork 0

Files

T

riley 6668969b03

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

2 lines

37 B

Systemverilog

Raw Blame History

`#include "instruction_classifier.v"