TroubleElectrical/FPGA_Uni
1
0 Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Fixed error where assignment was not within a combinational/sequential block

Browse Source
This commit is contained in:
riley committed 2026-09-08 18:23:27 +10:00
1 parent 60e5dae43b
commit 00d9e3de88
1 file changed
+19 -18
Download Patch File Download Diff File Expand all files Collapse all files
modules/instruction_classifier.sv
+19 -18
View File
@@ -3,23 +3,24 @@ module instruction_classifier(input logic op[5:0],
output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F, output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F,
output logic[0:0] M); output logic[0:0] M);
logic [6:0] OUT_1; always_comb begin
casez (op) logic [6:0] OUT_1;
6'b1?????: OUT_1 = 7'b1000000; casez (op)
6'b01????: OUT_1 = 7'b0100000; 6'b1?????: OUT_1 = 7'b1000000;
6'b001???: OUT_1 = 7'b0010000; 6'b01????: OUT_1 = 7'b0100000;
6'b0001??: OUT_1 = 7'b0001000; 6'b001???: OUT_1 = 7'b0010000;
6'b00001?: OUT_1 = 7'b0000100; 6'b0001??: OUT_1 = 7'b0001000;
6'b000001: OUT_1 = 7'b0000010; 6'b00001?: OUT_1 = 7'b0000100;
6'b000000: OUT_1 = 7'b0000001; 6'b000001: OUT_1 = 7'b0000010;
endcase 6'b000000: OUT_1 = 7'b0000001;
endcase
assign R = OUT_1[6];
assign B1 = OUT_1[5];
assign J = OUT_1[4];
assign B2 = OUT_1[3];
assign I = OUT_1[2];
assign F = OUT_1[1];
assign M = OUT_1[0];
R = OUT_1[6];
B1 = OUT_1[5];
J = OUT_1[4];
B2 = OUT_1[3];
I = OUT_1[2];
F = OUT_1[1];
M = OUT_1[0];
end
endmodule endmodule